Melanie D Typaldos

6366610, Apr 2, 2002

May 15, 1998

09/080336

Bruce A. Loyer - Austin TX
Melanie D. Typaldos - Buda TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H04B 1700

375225, 375354, 713600

An asynchronous receiver/transmitter provides autobauding with adjustment to a programmable baud rate. A baud divisor is calculated based on a detected size of a start bit. The asynchronous receiver/transmitter provides a plurality of baud divisor replacement registers, each register storing a baud divisor threshold and a baud divisor replacement. The baud divisor is compared to the plurality of programmed baud divisor thresholds. Based on the performed hardware comparison, the baud divisor is automatically replaced by a baud divisor replacement for a particular baud divisor range defined by a baud divisor threshold and including the baud divisor. The baud rate corresponding to this baud divisor replacement represents the appropriate baud rate. Autobauding with adjustment to a programmed baud rate corrects for measurement inaccuracies with respect to the start bit size. Autobauding with adjustment to a programmed baud rate also permits an asynchronous receiver/transmitter to reliably support high speed baud rates.

6385670, May 7, 2002

Jun 1, 1998

09/088133

David A. Spilo - Austin TX
Melanie D. Typaldos - Buda TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1314

710 26, 710 23, 375364, 375368, 370507

A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the âcompressiveâ DMA.

6850561, Feb 1, 2005

Jun 8, 2000

09/590353

Melanie D. Typaldos - Buda TX, US
Bruce A. Loyer - Austin TX, US
Hock-Koon Lee - Singapore, SG

Advanced Micro Devices, Inc. - Austin TX

H04B 346
H04L 2300

375225, 375377

A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.

63112353, Oct 30, 2001

Oct 31, 1998

9/184277

Melanie D. Typaldos - Buda TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1300

710 33

An asynchronous serial port provides increased serial throughput. In data frames comprising eight data bits, at least one bit may be disabled. The status and communication bits within the frame are moved into the locations of the disabled bits. The number of bits in the transmission data frame is thus reduced by the number of disabled data bits.

61451037, Nov 7, 2000

Apr 7, 1998

9/056509

Melanie D. Typaldos - Buda TX
Patrick E. Maupin - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

S06F 1100

714 55

A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value.

58621482, Jan 19, 1999

Feb 11, 1997

8/798249

Melanie D. Typaldos - Buda TX
Eric G. Chambers - Austin TX
Wade L. Williams - Austin TX

Advanced Micro Devices, Inc.

G06F 1100

371 221

A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode. This facilitates debugging of the code since the contents of the external memory may be examined, for example by an in-circuit emulator, in a less intrusive manner than the contents of the internal memory may be examined.

62601628, Jul 10, 2001

Oct 31, 1998

9/183915

Melanie D. Typaldos - Buda TX
David A. Spilo - Austin TX
Martin Schuessler - Pflugerville TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1100

714 55

A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.

58965491, Apr 20, 1999

Feb 4, 1997

8/807103

John P. Hansen - Austin TX
Melanie D. Typaldos - Buda TX
Louis R. Stott - Austin TX

Advanced Micro Devices, Inc.

G06F 300

395842

A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA). The microcontroller includes an execution unit, a DMA unit, one or more ASPs, and at least one input/output (I/O) pad formed upon a single monolithic semiconductor substrate. The execution unit is configured to execute instructions, preferably. times. 86 instructions. Each ASP is configurable to generate an internal DMA request signal, which effectuates a DMA transfer of serial communication data, and multiple DMA control signals. Each I/O pad is adapted to receive an external DMA request signal generated by a device external to the microcontroller. The DMA unit includes selection logic coupled to one or more DMA channel circuits. The selection logic receives the internal and external DMA request signals as well as the DMA control signals, and produces a DMA request signal for each DMA channel circuit.