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Mark M Moshayedi

from Newport Coast, CA
Age ~63
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Also known as:
Mehrdad Mark Moshayedi, Mehrdad M Moshayedi, Trus M Revocable, Moshayedi Mehrdad, Mehrdad I
Phone and address:
314 Amethyst Ave, Newport Beach, CA 92662
(949) 673-3325
Related to:
Badiollah Moshayedi, 62Alex Dariushnia, 55Ariane Moshayedi, 39Brian B Moshayedi, 35M Revocable TrusDesiree MoshayediAhmad DariushniaBijan B Moshayedi, 35Sophie K Moshayedi, 66Mike MoshayediKevin Moshayedi, 37Natalie MoshayediBadi MoshayediSemira Dariushnia, 58
Connected to:
Adrian M Moshe, 70Arlene T Moshe, 69Benjamin A Moshe, 39Diane L Moshe, 72Etty E Moshe, 56Eyal B Moshe, 41Menashe Moshe, 54Solomon L Moshe, 75Lisa A Mosheim, 64Judith A Moshell, 81

Mark Moshayedi Phones & Addresses

  • 314 Amethyst Ave, Newport Beach, CA 92662 (949) 673-3325
  • Newport Coast, CA
  • New York, NY
  • San Francisco, CA
  • Los Angeles, CA
  • Las Vegas, NV
  • Santa Ana, CA
  • Orange, CA

Work

Company: Space investment partners Jan 2018 Position: Co-founder and managing principle

Education

Degree: Master of Business Administration, Masters School / High School: Pepperdine University 1983 to 1985

Skills

Science • Computer Hardware

Industries

Computer Hardware

Resumes

Resumes

Mark Moshayedi Photo 1

Managing Partner

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Location:
14 Channel Vis, Newport Coast, CA 92657
Industry:
Computer Hardware
Work:
Space Investment Partners
Co-Founder and Managing Principle
Space Investment Partners
Managing Partner
Msm Global Ventures
Chief Executive Officer
Stec Oct 2012 - Sep 2013
Chief Executive Officer
Stec Sep 2007 - Oct 2012
President
Education:
Pepperdine University 1983 - 1985
Master of Business Administration, Masters Uc Irvine 1979 - 1982
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Science
Computer Hardware

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mark Moshayedi
President
Silicon Tech Inc
Mfg of Memory Storage Devices · Computer Storage Device Manufacturing
3009 Daimler St, Santa Ana, CA 92705
3001 Daimler St, Santa Ana, CA 92705
(949) 476-1130
Mark Moshayedi
Principal
Classic Investments
Investor · Investors, Nec
14 Channel Vis, Newport Beach, CA 92657
Mark Moshayedi
Chino Hills Mall LLC
Real Property Investment
13920 City Ctr Dr, Chino Hills, CA 91709
Mark Moshayedi
Managing
Global Oil and Gas LLC
Consulting
14 Channel Vis, Newport Beach, CA 92657
Mark Moshayedi
President & ceo, President, Director, Secretary, Vice-President, CTO
SimpleTech , Inc.
Electrical/Electronic Manufacturing · Mfg Computer Peripheral Equipment · Computer Storage Devices · Computer Storage Device Manufacturing · Computer Storage Device Mfg
3001 Daimler, Santa Ana, CA 92705
3001 Damler St, Santa Ana, CA 92705
2390 E Camelback Rd, Phoenix, AZ 85016
3009 Daimler St, Santa Ana, CA 92705
(949) 476-1180, (949) 476-1209, (949) 260-8219, (800) 367-7330

Publications

Us Patents

Multi-Function Module Incorporating Flash Memory And Enhanced I/O Interface That Can Translate Data From One Format Into Another Format For Subsequent Transmission To An External Device

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US Patent:
6442625, Aug 27, 2002
Filed:
Oct 30, 2000
Appl. No.:
09/702276
Inventors:
Brian H. Robinson - San Pedro CA
Mark Moshayedi - Orange CA
Assignee:
SimpleTech, Inc. - Santa Ana CA
International Classification:
G06F 1310
US Classification:
710 8, 710 10, 710 11
Abstract:
A module incorporating a flash memory and a flash memory controller. The flash memory controller receives data via a first interface which can be a PCMCIA type interface. The data is then stored in the flash memory. The controller is adapted to be able to selectively recall the data from the flash memory and transmit the data to one or more recipient devices via the PCMCIA type interface or by an alternate interface. The module incorporates a user input device that, when manipulated by the user, induces the controller to send the data via the alternate interface. In one embodiment, the alternate interface is comprised of a GSM interface which allows data stored in the flash memory to be transmitted via a cellular telephone to a pre-selected telephone number by the user manipulating the user input device.

Multi-Function Module Incorporating Flash Memory And Enhanced I/O Interface That Can Translate Data From One Format Into Another Format For Subsequent Transmission To An External Device

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US Patent:
6728794, Apr 27, 2004
Filed:
Aug 2, 2002
Appl. No.:
10/211947
Inventors:
Brian H. Robinson - San Pedro CA
Mark Moshayedi - Orange CA
Assignee:
Simple Tech, Inc. - Santa Ana CA
International Classification:
G06F 1310
US Classification:
710 8, 710 10, 710 11
Abstract:
A module incorporating a flash memory and a flash memory controller. The flash memory controller receives data via a first interface which can be a PCMCIA type interface. The data is then stored in the flash memory. The controller is adapted to be able to selectively recall the data from the flash memory and transmit the data to one or more recipient devices via the PCMCIA type interface or by an alternate interface. The module incorporates a user input device that, when manipulated by the user, induces the controller to send the data via the alternate interface. In one embodiment, the alternate interface is comprised of a GSM interface which allows data stored in the flash memory to be transmitted via a cellular telephone to a pre-selected telephone number by the user manipulating the user input device.

Stack Arrangements Of Chips And Interconnecting Members

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US Patent:
6762487, Jul 13, 2004
Filed:
Apr 19, 2002
Appl. No.:
10/127343
Inventors:
Mark Moshayedi - Orange CA
Assignee:
SimpleTech, Inc. - Santa Ana CA
International Classification:
H01L 2348
US Classification:
257686, 257685, 257777, 257723, 257680, 257774, 257698, 257724, 257778, 257738, 257737, 438108, 438109, 361396, 361393, 361414, 361403, 361415, 361412, 439 69, 439 74
Abstract:
A method and structures for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One aspect is a stack of two chips with a preformed interconnecting support connecting the two chips and with space for mounting a third chip to at least one of the other two chips in an interstitial space between the two chips and inside the support. Another aspect is a chip stack where two smaller chips are interconnected a larger third chip on both sides thereof and further with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another aspect is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.

Multi-Function Interface Module

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US Patent:
6981071, Dec 27, 2005
Filed:
Mar 8, 2004
Appl. No.:
10/793826
Inventors:
Brian H. Robinson - San Pedro CA, US
Mark Moshayedi - Newport Coast CA, US
Assignee:
SimpleTech, Inc. - Santa Ana CA
International Classification:
G06F013/10
US Classification:
710 8, 710 10, 710 11
Abstract:
A multi-function interface module having at least one interface and a controller for manipulating input and output data.

Systems And Methods For Stacking Chip Components

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US Patent:
7057270, Jun 6, 2006
Filed:
May 25, 2004
Appl. No.:
10/853865
Inventors:
Mark Moshayedi - Orange CA, US
Assignee:
SimpleTech, Inc. - Santa Ana CA
International Classification:
H01L 23/48
H01L 23/52
US Classification:
257686, 257685, 257777, 257723, 257680, 257774, 257698, 257724, 257780, 257734, 257737, 257738, 257778, 361393, 361414, 361403, 361415, 361412, 439 69, 439 74, 438108, 438109
Abstract:
Systems and methods for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Another embodiment provides a method for stacking chips where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another embodiment is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.

System And Method For Preventing Data Corruption In Solid-State Memory Devices After A Power Failure

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US Patent:
7107480, Sep 12, 2006
Filed:
Dec 20, 2001
Appl. No.:
10/032332
Inventors:
Mark Moshayedi - Orange CA, US
Brian H. Robinson - San Pedro CA, US
Assignee:
SimpleTech, Inc. - Santa Ana CA
International Classification:
G06F 11/00
US Classification:
714 2
Abstract:
A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.

Protection Against Data Corruption Due To Power Failure In Solid-State Memory Device

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US Patent:
7409590, Aug 5, 2008
Filed:
Jul 28, 2006
Appl. No.:
11/494986
Inventors:
Mark Moshayedi - Newport Coast CA, US
Brian Robinson - San Pedro CA, US
Assignee:
STEC, Inc. - Santa Ana CA
International Classification:
G06F 11/00
US Classification:
714 20
Abstract:
A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.

Staged-Backup Flash Backed Dram Module

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US Patent:
7830732, Nov 9, 2010
Filed:
Feb 11, 2009
Appl. No.:
12/369027
Inventors:
Mark Moshayedi - Newport Coast CA, US
Douglas Finke - Orange CA, US
Assignee:
STEC, Inc. - Santa Ana CA
International Classification:
G11C 7/00
US Classification:
3651892, 36518917, 365227
Abstract:
A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.
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Mark M Moshayedi from Newport Coast, CA, age ~63 Get Report