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Mehmet Ali Tan

from Irvine, CA
Age ~65
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Also known as:
Mehmet A Tan, Hemmet A Tan, Mehmet A Pan, Temeria Mincey
Phone and address:
252 Greenmoor, Irvine, CA 92614
(949) 551-5302
Related to:
Cleotilde G Cruz, 72Sakire M Tan, 55Joshua Tan, 42Alexander T Tan, 70Yunus Tan, 33Ece TanBismarck S Tan, 51Erwin J Tan, 50
Connected to:
Ainah U Tan, 38Al T Tan, 71Alan H Tan, 48Albert J Tan, 43Alena Y Tan, 52Alfian Tan, 52Amanda N Tan, 41Analysa V Tan, 35Anastasia Tan, 37Andi Tan, 35

Mehmet Tan Phones & Addresses

  • 252 Greenmoor, Irvine, CA 92614 (949) 551-5302
  • Petaluma, CA
  • Newport Beach, CA
  • Tustin, CA
  • San Diego, CA
  • Orange, CA

Resumes

Resumes

Mehmet Tan Photo 1

Senior Principal Electrical Engineer

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Location:
Irvine, CA
Industry:
Semiconductors
Work:
Microsemi Corporation Mar 1, 2014 - Nov 2017
Principal Analog Design Engineer
Maxim Integrated Jan 2007 - Feb 2014
Senior Principal Member of Technical Staff, Ic Design
Ess Technology, Inc. 2003 - 2007
Senior Principal Design Engineer
2003 - 2007
Senior Principal Electrical Engineer
Education:
University of Minnesota 1984 - 1988
Doctorates, Doctor of Philosophy, Electrical Engineering Istanbul Technical University 1981 - 1984
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electronics Engineering, Electronics Istanbul Technical University 1975 - 1980
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Analog Filters
Cmos
Mixed Signal
Analog Circuit Design
Asic
Ic
Analog
Integrated Circuit Design
Pll
Semiconductors
Bicmos
Signal Integrity
Circuit Design
Cadence
Cadence Virtuoso
Mixed Signal Ic Design
Semiconductor Industry
Simulations
Vco
Integrated Circuits
Interests:
Social Services
Children
Enjoy Playing and Listening Music
Recreational Tennis Player
Economic Empowerment
Environment
Education
Avid Reader
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Human Rights
Health
Languages:
English
Turkish
Mehmet Tan Photo 2

Mehmet Tan

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Publications

Us Patents

Reduced Complexity Linear Phase Detector

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US Patent:
6806740, Oct 19, 2004
Filed:
May 30, 2003
Appl. No.:
10/452661
Inventors:
Mehmet Ali Tan - Irvine CA
Daniel Chan - Huntington Beach CA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03D 900
US Classification:
327 2, 327 12
Abstract:
A linear phase detector includes first, second and third latches connected in series, each of the latches having a data input, a data output and a clock input, and further includes reference signal generation circuitry and error signal generation circuitry. The reference signal generation circuitry has at least a first input coupled to the data output of the second latch and a second input coupled to the data output of the third latch. The error signal generation circuitry has at least a first input coupled to the data input of the first latch and a second input coupled to the data output of the second latch, and is configured to generate an output that is indicative, relative to the reference signal, of the phase error of a clock signal. The linear phase detector is preferably configured such that a first version of the clock signal is applied to the clock inputs of the first and third latches, and a second version of the clock signal is applied to the clock input of the second latch, the first and second versions being complementary relative to one another. The linear phase detector in an illustrative embodiment exhibits a linearity substantially equivalent to that associated with a conventional four-latch Hogge detector.

Phase-Locked Loop With Loop Select Signal Based Switching Between Frequency Detection And Phase Detection

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US Patent:
6812797, Nov 2, 2004
Filed:
May 30, 2003
Appl. No.:
10/452657
Inventors:
Geert Adolf De Veirman - Corona del Mar CA
Mehmet Ali Tan - Irvine CA
Xinyu Chen - Irvine CA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03L 7087
US Classification:
331 11, 331 17, 331 25, 327156, 327157
Abstract:
A phase-locked loop (PLL) includes at least first and second loops, and loop selection circuitry coupled to the first and second loops, the loop selection circuitry being responsive to at least one loop select signal to control transition from an operating mode of one of the first and second loops to an operating mode of the other of the first and second loops. In an illustrative embodiment, the PLL comprises a dual-loop PLL with the first and second loops corresponding to respective frequency and phase loops, and the loop selection circuitry is configured such that the loop select signal as applied to a control input of a current-generating component of the first loop represents a delayed and inverted version of the loop select signal as applied to a control input of a current-generating component of the second loop.

Circuit For Controlling Field Effect Device Transconductance

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US Patent:
6828831, Dec 7, 2004
Filed:
May 30, 2003
Appl. No.:
10/452089
Inventors:
Mehmet Ali Tan - Irvine CA
Geert Adolf DeVeirman - Corona del Mar CA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H02M 1100
US Classification:
327103
Abstract:
A transconductance control circuit includes a master device having first and second field effect devices coupled to respective first and second current sources, a reference device coupled to a third current source, and comparison circuitry. The comparison circuitry includes at least first, second and third inputs and at least one output, with the first input configured to receive a reference signal associated with the reference device, the second and third inputs coupled to respective terminals of the first and second field effect devices, and the output coupled to current control inputs of one or more of the current sources. The transconductance control circuit provides a feedback control arrangement in which, for example, the comparison circuitry output is utilized to adjust one or more of the current sources such that a difference signal V between voltages at the respective terminals of the first and second field effect devices converges to a reference signal V. As a result, the transconductance g of the first field effect device converges to the conductance of the reference device.

Programmable Voltage-Controlled Oscillator With Self-Calibration Feature

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US Patent:
6842082, Jan 11, 2005
Filed:
May 30, 2003
Appl. No.:
10/452091
Inventors:
Mehmet Ali Tan - Irvine CA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03B 504
H03B 524
H03L 100
US Classification:
331175, 331 57
Abstract:
A programmable voltage-controlled oscillator includes a ring oscillator having a number of selectable delay stages, and a resistor value detection circuit configurable for coupling to an external resistor. The resistor value detection circuit includes at least one internal resistor and is operative to generate, based at least in part on a value of the external resistor, an output signal indicative of a value of the internal resistor. The output signal is utilizable in controlling an oscillation frequency of the ring oscillator based at least in part on selection of one or more of the selectable delay stages. The voltage-controlled oscillator may be utilized in a phase-locked loop of clock recovery circuit in an integrated circuit, and in numerous other applications.

Resistor Value Detection Circuit

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US Patent:
6937028, Aug 30, 2005
Filed:
May 30, 2003
Appl. No.:
10/452329
Inventors:
Mehmet Ali Tan - Irvine CA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G01R035/00
G01R027/08
US Classification:
324601, 324691
Abstract:
A resistor detection circuit configurable for coupling to an external resistor of an integrated circuit or other type of circuit includes at least one internal resistor, and comparison circuitry associated with the internal resistor. The comparison circuitry is operative to generate, based at least in part on a value of the external resistor, an output indicative of a value of the internal resistor. The output generated by the comparison circuitry may comprise an encoded digital output signal representative of the value of the internal resistor.

Multi-Stage Amplifier With Switching Circuitry

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US Patent:
7199654, Apr 3, 2007
Filed:
Jun 17, 2005
Appl. No.:
11/155296
Inventors:
Jaifu Luo - Irvine CA, US
Rajagopal Sundararaman - Mission Viejo CA, US
Mehmet Ali Tan - Irvine CA, US
Assignee:
ESS Technology, Inc. - Fremont CA
International Classification:
H03F 1/02
US Classification:
330 9, 330 51
Abstract:
Disclosed are a multi-stage amplifier circuit, a method of operating a multi-stage amplifier circuit, and a device with the multi-stage amplifier circuit. The amplifier circuit technology includes an operational amplifier shared among multiple stages and switching circuitry. The various switching circuitry switches among elements to provide different input signals and different feedback to the shared operational amplifier at the different stages of operation of the amplifier circuit. The various switching circuitry also stores and discharges charge at one or more operational amplifier inputs.

Self-Calibrating Anti-Blooming Circuit For Cmos Image Sensor Having A Spillover Protection Performance In Response To A Spillover Condition

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US Patent:
7381936, Jun 3, 2008
Filed:
Oct 29, 2004
Appl. No.:
10/975474
Inventors:
Mehmet Ali Tan - Irvine CA, US
Jiafu Luo - Thousand Oaks CA, US
Assignee:
ESS Technology, Inc. - Fremont CA
International Classification:
H01L 27/00
US Classification:
2502081, 250214 R
Abstract:
A method and apparatus to provide blooming protection for a pixel in an array while extending dynamic range.

System And Method For Generating Self-Aligned Clock Signals For Consecutive Circuit Operations

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US Patent:
20070069794, Mar 29, 2007
Filed:
Sep 28, 2005
Appl. No.:
11/238421
Inventors:
Mehmet Tan - Irvine CA, US
Assignee:
ESS Technology, Inc. - Fremont CA
International Classification:
G06F 1/04
US Classification:
327291000
Abstract:
A system and method of generating a clock signal are provided for driving a plurality of consecutive circuit phase operations. The method includes generating a clock signal, transmitting the clock signal to one circuit phase operation, and transmitting another clock signal to a previous circuit phase operation. A circuit configured according to the invention can clock a plurality of consecutive circuit phase operations with a single master clock, where each circuit phase generates a clock signal to clock a previous phase, obviating connections from a master clock to multiple phases.
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Mehmet Ali Tan from Irvine, CA, age ~65 Get Report