Maynard C Falconer

6346842, Feb 12, 2002

Dec 12, 1997

08/989836

Maynard C. Falconer - Hillsboro OR

Intel Corporation - Santa Clara CA

H03H 1126

327277, 327384, 327290, 327565

A variable delay path circuit having delay paths of different lengths is disclosed. Any of the delay paths can be selected to match the operating conditions of the system. In one embodiment of the invention, a delay path circuit having two delay paths connects a driver and receiver. Each of the two delay paths contains sites at both ends for placing zero ohm resistors, solder or copper slugs. To select one of the two delay paths, zero ohm resistors, solder or copper slugs are placed in the sites at the ends of the desired delay path. The delay is then dictated by the time it takes for a clocking signal to travel the length of selected delay path.

6577179, Jun 10, 2003

Nov 15, 1999

09/440494

Maynard C. Falconer - Portland OR

Intel Corporation - Santa Clara CA

H02J 338

327530, 327362, 326 30, 333 173

A method of adjusting a circuit operating characteristic. The method includes generating a first signal for application to a reference termination. The method then includes generating a first voltage based on the first signal at a first point on the reference termination and generating a second voltage based on the first signal at a second point on the reference termination. The method also includes adjusting an operating characteristic based upon the first voltage and the second voltage. In an embodiment, the operating characteristic can be an impedance.

6587323, Jul 1, 2003

Dec 22, 1999

09/470925

Maynard C. Falconer - Portland OR

Intel Corporation - Santa Clara CA

H02H 300

361 90, 361 18, 361 58

A circuit including a power supply plane, a ground supply plane, and a signal source that generates reference voltage signals and a first signal. The signal source includes a driver adapted to generate a first signal to the receiver, the first signal having a present and a previous voltage levels. The signal source also includes a low reference voltage generator and a high reference voltage generator, each producing a low reference voltage signal and a high reference voltage signal, respectively, from a low reference output and a high reference output, respectively. The high reference output and the low reference output are coupled to the ground plane and the power supply plane, respectively. The high reference voltage generator and the low reference generator are capable of communicating the high reference voltage signal and the low reference voltage signal to the receiver.

6741165, May 25, 2004

Jun 4, 1999

09/325947

Craig Langfahl - Mountain View CA
Matthew Eldon Hoekstra - Forest Grove OR
Maynard Falconer - Portland OR

Intel Corporation - Santa Clara CA

B60R 2510

3404261, 34042611, 3404255, 340937, 701 36, 307 102, 348148, 348143, 348152

A system, apparatus and method are provided for using an imaging device for surveillance. According to one embodiment, a sensor is triggered when a situation occurs, the triggered sensor is detected, the imaging device is turned in the direction of the triggered sensor, and the imaging device is activated to capture an image.

6774819, Aug 10, 2004

Jul 23, 1999

09/361500

Maynard Falconer - Portland OR

Intel Corporation - Santa Clara CA

H03K 1794

341 22, 345168, 200512, 400712

A flexible keyboard formed from a grid of flexible wires. Crosspoints between the wires are used to define characters to be selected via the keyboard. The characters are selected by pressing at a location, pressing two wires against one another.

6794895, Sep 21, 2004

Jun 27, 2002

10/186005

Maynard C. Falconer - Portland OR

Intel Corporation - Santa Clara CA

H03K 19003

326 30, 326 26, 333 24 R

A technique for reducing power consumption in voltage and current steered differential busses that transmit and receive encoded signals is described. A circuit is used to save power in the static state. The circuit blocks static current flow, but allows the frequency components associated with the signaling band.

7076677, Jul 11, 2006

Dec 30, 2002

10/330053

Maynard C. Falconer - Portland OR, US
Zane A. Ball - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 1/12
G06F 1/04
G11C 7/00
G11C 7/22

713400, 713500, 713502, 713401, 713600, 36518901, 365205

A source synchronous bus system is provided with a bus; a first device connected to the bus, having a driver to drive data and strobe signals, via the bus; and a second device connected to the bus, having a receiver to receive data and the strobe signals from the bus, and to select one of rising and falling edges of the strobe signals to latch a corresponding one of rising and falling edges of the data received from the bus, for subsequent data processing functions in order to compensate for systematic differences between rising and falling edges of the data received, via the bus.

8503678, Aug 6, 2013

Dec 23, 2009

12/646823

Maynard C. Falconer - Portland OR, US
Christopher P. Mozak - Beaverton OR, US
Adam J. Norman - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 21/00

380268, 713 2

Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.