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Matthew S Wingren

from Pine Island, MN
Age ~64
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Also known as:
Unicorn West Wingren, Matt S Wingren
Phone and address:
8937 115Th St, Pine Island, MN 55963
(507) 356-8098
Related to:
Maxwell Wingren, 32Andrew Wingren, 35Paul R Wingren, 66Sarah L WingrenNola R Wingren, 62Ralf H WingrenAllison Wingren, 39Audrey WingrenAmanda M Wingren, 36Gretchen J Wingren, 58
Connected to:
Robert N Wingren, 64Carole S Wingrove, 61Catherine M Wingrove, 61Diana M Wingrove, 82Fiona V Wingrove, 89Jessica R Wingrove, 38Kenneth B Wingrove, 52Mary E Wingrove, 74Nicholas R Wingrove, 96Ronald L Wingrove, 58

Matthew Wingren Phones & Addresses

  • 8937 115Th St, Pine Island, MN 55963 (507) 356-8098
  • 2607 62Nd St, Rochester, MN 55901 (507) 529-1018
  • 830 Buckboard Ln, Idaho Falls, ID 83402 (208) 529-8659
  • 12188 Olalla Valley Rd SE, Olalla, WA 98359 (253) 529-8659
  • Bremerton, WA
  • Charter Oak, IA
  • 8937 115Th St NW, Pine Island, MN 55963 (507) 317-5013

Work

Company: Romark corporation - Bremerton, WA Jun 2004 Position: Cnc machine operator, job detailer

Education

School / High School: TACOMA COMMUNITY COLLEGE- Tacoma, WA 1998

Skills

Read and Understand Blueprints • Computer Aided Drafting & Design • Strong Shop Math Skills • Good Hand/Eye Coordination • Safety Coordinator • Modify/Edit Programs • Machine Operating • Set-ups/Tear-downs • Reverse Engineering • Inventory Control • Quality Assurance • Shipping/Receiving • Task Scheduling • Material Ordering

Industries

Computer Networking

Resumes

Resumes

Matthew Wingren Photo 1

Systems Architect

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Location:
8937 115Th St, Pine Island, MN 55963
Industry:
Computer Networking
Work:
Brandhoot
Systems Architect
Matthew Wingren
Systems and Programming Consultant
Brocade 2007 - Sep 2013
Senior Asic Engineer
Ciber 2006 - 2007
Consulting Engineer
Lsi Corporation 2001 - 2006
Senior Design Engineer
Education:
University of Washington 1994 - 1997
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering, Electronics
Skills:
Verilog
Debugging
Perl
Python
Embedded Systems
Programming
Systemverilog
C
Functional Verification
C++
Analog
Unix
Static Timing Analysis
Hardware Architecture
Shell Scripting
Php
Java
Object Oriented Software
Web Development
Hardware Design
Problem Solving
Photography
Portrait Photography
Web Application Design
Sql
Power Plant Operations
Animal Husbandry
Classroom Instruction
Seminar Presentations
System Verification
Objective C
Swift
Ios Development
Matthew Wingren Photo 2

Matthew Wingren Mesa, AZ

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Work:
Romark Corporation
Bremerton, WA
Jun 2004 to Sep 2012
CNC Machine Operator, Job Detailer
Lloyd Enterprises, LLC
Federal Way, WA
Apr 2004 to May 2004
Underground Infrastructure Laborer
Romark Corportation
Bremerton, WA
Dec 2003 to Feb 2004
Sawyer, Drill Press Operator
Dream Maker Kitchen & Bath
Gig Harbor, WA
Aug 2002 to Jan 2003
Technician's Assistant
Commercial Floor Services, Inc
Gig Harbor, WA
Oct 2001 to Apr 2002
Owner/Operator
Commercial Building Maintenance, Inc
Gig Harbor, WA
Aug 2001 to Oct 2001
Carpet/Floor Cleaning Technician
Milgard Manufacturing
Tacoma, WA
Jul 2000 to Jul 2001
Assembly Line Worker, Machine Operator
Skills:
Read and Understand Blueprints, Computer Aided Drafting & Design, Strong Shop Math Skills, Good Hand/Eye Coordination, Safety Coordinator, Modify/Edit Programs, Machine Operating, Set-ups/Tear-downs, Reverse Engineering, Inventory Control, Quality Assurance, Shipping/Receiving, Task Scheduling, Material Ordering

Publications

Us Patents

Custom Clock Interconnects On A Standardized Silicon Platform

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US Patent:
6910201, Jun 21, 2005
Filed:
Sep 17, 2003
Appl. No.:
10/664137
Inventors:
Jonathan William Byrn - Kasson MN, US
James Arnold Jensen - Eagan MN, US
Matthew Scott Wingren - Rochester MN, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
H01L027/10
US Classification:
716 17, 257204
Abstract:
A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

Simplified Process To Design Integrated Circuits

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US Patent:
7055113, May 30, 2006
Filed:
Dec 31, 2002
Appl. No.:
10/335360
Inventors:
Robert Neal Carlton Broberg, III - Rochester MN, US
Jonathan William Byrn - Kasson MN, US
Gary Scott Delp - Rochester MN, US
Michael K. Eneboe - San Jose CA, US
Gary Paul McClannahan - Rochester MN, US
George Wayne Nation - Eyota MN, US
Paul Gary Reuland - Rochester MN, US
Thomas Sandoval - Los Gatos CA, US
Matthew Scott Wingren - Rochester MN, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 18
Abstract:
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Automatic Generation Of Correct Minimal Clocking Constraints For A Semiconductor Product

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US Patent:
7380229, May 27, 2008
Filed:
Jun 13, 2005
Appl. No.:
11/151043
Inventors:
Jonathan W. Byrn - Kasson MN, US
Matthew S. Wingren - Rochester MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 7, 716 18, 703 16
Abstract:
A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e. g. , clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

Suite Of Tools To Design Integrated Circuits

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US Patent:
7430725, Sep 30, 2008
Filed:
Jun 18, 2005
Appl. No.:
11/156319
Inventors:
Robert Neal Carlton Broberg, III - Rochester MN, US
Jonathan William Byrn - Kasson MN, US
Gary Scott Delp - Rochester MN, US
Michael K. Eneboe - San Jose CA, US
Gary Paul McClannahan - Rochester MN, US
George Wayne Nation - Eyota MN, US
Paul Gary Reuland - Rochester MN, US
Thomas Sandoval - Los Gatos CA, US
Matthew Scott Wingren - Rochester MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 18
Abstract:
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Placement Of Configurable Input/Output Buffer Structures During Design Of Integrated Circuits

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US Patent:
20040128626, Jul 1, 2004
Filed:
Dec 31, 2002
Appl. No.:
10/334568
Inventors:
Matthew Wingren - Rochester MN, US
George Nation - Eyota MN, US
Gary Delp - Rochester MN, US
Jonathan Byrn - Kasson MN, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
US Classification:
716/001000
Abstract:
A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.

Method For Creating Constraints For Integrated Circuit Design Closure

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US Patent:
20070033557, Feb 8, 2007
Filed:
Aug 8, 2005
Appl. No.:
11/199434
Inventors:
Jonathan Byrn - Kasson MN, US
Matthew Wingren - Rochester MN, US
Paul Reuland - Rochester MN, US
International Classification:
G06F 17/50
US Classification:
716005000, 716006000
Abstract:
A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to create orthogonal constraint sets which are tuned for both a specific tool and a positional use of the specific tool within the design flow.
Control profile
Matthew S Wingren from Pine Island, MN, age ~64 Get Report