Matthew J Reagor

20220231690, Jul 21, 2022

Aug 24, 2021

17/410042

- Berkeley CA, US
Nicolas Didier - Berkeley CA, US
Marcus Palmer da Silva - Lafayette CA, US
Chad Tyler Rigetti - Walnut Creek CA, US
Matthew J. Reagor - Corte Madera CA, US
Shane Arthur Caldwell - Oakland CA, US
Nikolas Anton Tezak - Oakland CA, US
Colm Andrew Ryan - Albany CA, US
Sabrina Sae Byul Hong - Oakland CA, US
Prasahnt Sivarajah - Emeryville CA, US
Alexander Papageorge - San Francisco CA, US
Deanna Margo Abrams - Oakland CA, US

Rigetti & Co, LLC - Berkeley CA

H03K 19/195
G06N 10/00

In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

20210342729, Nov 4, 2021

Dec 11, 2020

17/119089

- Berkeley CA, US
Maxwell Benjamin Block - Oakland CA, US
Benjamin Jacob Bloom - Oakland CA, US
Matthew J. Reagor - Corte Madera CA, US
Alexander Papageorge - San Francisco CA, US
Kamal Yadav - Fremont CA, US
Nasser Alidoust - Berkeley CA, US
Colm Andrew Ryan - Albany CA, US
Shane Arthur Caldwell - Oakland CA, US
Yuvraj Mohan - Fremont CA, US
Anthony Polloreno - Carlsbad CA, US
John Morrison Macaulay - Emeryville CA, US
Blake Robert Johnson - El Cerrito CA, US

Rigetti & Co, Inc. - Berkeley CA

G06N 10/00
G06F 15/78

In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.

20210056454, Feb 25, 2021

Apr 6, 2020

16/841300

- Berkeley CA, US
Shane Arthur CALDWELL - Oakland CA, US
Michael James CURTIS - Sacramento CA, US
Matthew J. REAGOR - Corte Madera CA, US
Chad Tyler RIGETTI - Walnut Creek CA, US
Eyob A. SETE - Walnut Creek CA, US
William J. ZENG - Berkeley CA, US
Peter Jonathan KARALEKAS - Berkeley CA, US
Nikolas Anton TEZAK - Oakland CA, US
Nasser ALIDOUST - Berkeley CA, US

Rigetti & Co, Inc. - Berkeley CA

G06N 10/00
H03K 19/195

In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

20200204181, Jun 25, 2020

Oct 25, 2019

16/663809

- Berkeley CA, US
Nicolas Didier - Berkeley CA, US
Marcus Palmer da Silva - Lafayette CA, US
Chad Tyler Rigetti - Walnut Creek CA, US
Matthew J. Reagor - Corte Madera CA, US
Shane Arthur Caldwell - Oakland CA, US
Nikolas Anton Tezak - Oakland CA, US
Colm Andrew Ryan - Albany CA, US
Sabrina Sae Byul Hong - Oakland CA, US
Prasahnt Sivarajah - Emeryville CA, US
Alexander Papageorge - San Francisco CA, US
Deanna Margo Abrams - Oakland CA, US

Rigetti & Co, Inc. - Berkeley CA

H03K 19/195
G06N 10/00

In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

20200050958, Feb 13, 2020

Apr 22, 2019

16/390964

- Berkeley CA, US
Shane Arthur Caldwell - Oakland CA, US
Michael James Curtis - Sacramento CA, US
Matthew J. Reagor - Corte Madera CA, US
Chad Tyler Rigetti - Walnut Creek CA, US
Eyob A. Sete - Walnut Creek CA, US
William J. Zeng - Berkeley CA, US
Peter Jonathan Karalekas - Berkeley CA, US
Nikolas Anton Tezak - Oakland CA, US
Nasser Alidoust - Berkeley CA, US

Rigetti & Co, Inc. - Berkeley CA

G06N 10/00
H03K 19/195

In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

20190007051, Jan 3, 2019

Jun 19, 2018

16/012551

- Berkeley CA, US
Nicolas Didier - Berkeley CA, US
Marcus Palmer da Silva - Lafayette CA, US
Chad Tyler Rigetti - Emeryville CA, US
Matthew J. Reagor - Corte Madera CA, US
Shane Arthur Caldwell - Oakland CA, US
Nikolas Anton Tezak - Oakland CA, US
Colm Andrew Ryan - Albany CA, US
Sabrina Sae Byul Hong - Oakland CA, US
Prasahnt Sivarajah - Emeryville CA, US
Alexander Papageorge - San Francisco CA, US
Deanna Margo Abrams - Oakland CA, US

Rigetti & Co, Inc. - Berkeley CA

H03K 19/195
G06N 99/00

In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

20180260731, Sep 13, 2018

Mar 7, 2018

15/914662

- Berkeley CA, US
Nicholas C. Rubin - Berkeley CA, US
Matthew J. Reagor - Corte Madera CA, US
Michael Justin Gerchick Scheer - Oakland CA, US

Rigetti & Co., Inc. - Berkeley CA

G06N 99/00
G06F 17/17
G06F 15/82

In a general aspect, a computing system is configured to execute a quantum approximate optimization algorithm. In some aspects, a control system identifies a pair of qubit devices in a quantum processor. The quantum processor includes a connection that provides coupling between the pair of qubit devices. ZZ coupling between the pair of qubit devices is activated to execute a cost function defined in the quantum approximate optimization algorithm. The cost function is associated with a maximum cut problem, and the ZZ coupling is activated by allowing the pair of qubits to evolve under a natural Hamiltonian for a time period τ. One or more of the pair of qubit devices is measured to obtain an output from an execution of the quantum approximate optimization algorithm.

20180260732, Sep 13, 2018

Mar 9, 2018

15/916367

- Berkeley CA, US
Shane Arthur Caldwell - Oakland CA, US
Michael James Curtis - Sacramento CA, US
Matthew J. Reagor - Corte Madera CA, US
Chad Tyler Rigetti - Emeryville CA, US
Eyob A. Sete - Walnut Creek CA, US
William J. Zeng - Berkeley CA, US
Peter Jonathan Karalekas - Berkeley CA, US
Nikolas Anton Tezak - Berkeley CA, US
Nasser Alidoust - Berkeley CA, US

Rigetti & Co, Inc. - Berkeley CA

G06N 99/00
H03K 19/195

In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.