Resumes
Resumes
Matthew Fichtenbaum Phones & Addresses
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46 Sleigh Rd, Chelmsford, MA 01824 (978) 256-8546
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Carlisle, MA
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
Emails
Publications
Us Patents
Method Of And Apparatus For Multiplexed Automatic Testing Of Electronic Circuits And The Like
View pageUS Patent:
46203044, Oct 28, 1986
Filed:
Mar 13, 1985
Appl. No.:
6/710535
Inventors:
James J. Faran - Lincoln MA
Matthew L. Fichtenbaum - Chelmsford MA
William C. Kabele - Littleton MA
Matthew L. Fichtenbaum - Chelmsford MA
William C. Kabele - Littleton MA
Assignee:
Gen Rad, Inc. - Concord MA
International Classification:
G01R 3128
US Classification:
371 20
Abstract:
This disclosure is concerned with the automatic testing of electronic circuits and assemblies and the like containing large numbers of nodes, with reduced replications of test instruments and thus significantly reduced cost, through permitting a number of driver-sensors to be selectively switched to a larger number of nodes of the circuit being tested in accordance with a method of specifying and allocating the connections of the nodes of that circuit to the pins associated with each driver-sensor (or group thereof) that insures that no conflicts arise in connecting the driver-sensors to various groups of nodes for carrying out the desired tests.
Slip Detection During Bit-Error-Rate Measurement
View pageUS Patent:
52822117, Jan 25, 1994
Filed:
Oct 15, 1991
Appl. No.:
7/776850
Inventors:
Matthew L. Fichtenbaum - Chelmsford MA
Assignee:
GenRad, Inc. - Concord MA
International Classification:
G06F 1100
US Classification:
371 54
Abstract:
A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90). At the same time, another XOR GATE (70) compares the output of the channel or of one of the other delay circuits (38, 42, and 44) with the pseudo-random-number-generator output, and a decoder (80) generates a slip-indicating output when a counter (76), which counts the number of consecutive matches that the latter XOR GATE (70) detects, indicates that the output of the channel or other delay circuit (38, 42, or 44) has matched the output-side pseudo-random-number-generator output a number of times in a row indicative of the likelihood of a frame slip. In response, a slip counter (92) is incremented and the shift register (88) cleared to avoid counting as ordinary bit errors mismatches that occurred in the CENTER signal during the matching sequence in the other signal.
Phase Change Detection Method Of And Apparatus For Current-Tracing The Location Of Faults On Printed Circuit Boards And Similar Systems
View pageUS Patent:
41863380, Jan 29, 1980
Filed:
Dec 16, 1976
Appl. No.:
5/751103
Inventors:
Matthew L. Fichtenbaum - Chelmsford MA
Assignee:
GenRad, Inc. - Concord MA
International Classification:
G01R 3108
US Classification:
324 52
Abstract:
This disclosure is concerned with novel current-tracing of short circuits in printed circuit boards and similar systems by novel test excitation of the conductors with tracing of the phase polarities of the fields generated therein.