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Mathieu Tallegas Phones & Addresses

  • Duvall, WA
  • Issaquah, WA
  • 4665 234Th Ave SE, Sammamish, WA 98075
  • 715 Saint Charles Rd, Veradale, WA 99037
  • Spokane Valley, WA
  • Kiona, WA

Publications

Us Patents

Non-Blocking, Multi-Context Pipelined Processor

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US Patent:
7080238, Jul 18, 2006
Filed:
Aug 30, 2001
Appl. No.:
09/941528
Inventors:
Werner Van Hoof - Veradale WA, US
Jerrold Wheeler - Spokane WA, US
Mathieu Tallegas - Veradale WA, US
Assignee:
Alcatel Internetworking, (PE), Inc. - Spokane WA
International Classification:
G06F 9/38
US Classification:
712234, 712 1
Abstract:
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Non-Blocking, Multi-Context Pipelined Processor

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US Patent:
7797513, Sep 14, 2010
Filed:
Jul 3, 2006
Appl. No.:
11/428464
Inventors:
Werner Van Hoof - 2630 Aartselaar, BE
Jerrold Wheeler - Spokane WA, US
Mathieu Tallegas - Veradale WA, US
International Classification:
G06F 9/38
US Classification:
712 36, 712 1, 712234
Abstract:
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Stackable Lookup Engines

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US Patent:
20010037396, Nov 1, 2001
Filed:
Jan 18, 2001
Appl. No.:
09/764943
Inventors:
Mathieu Tallegas - Veradale WA, US
International Classification:
G06F015/16
US Classification:
709/230000
Abstract:
Multiple lookup engines stacked upon one another in a single data communication switch. The lookup engine at the top of the stack transmits its result to the neighboring downstream lookup engine which either validates and transmits the received result or its own result based on the quality of its match. The result preferably indicates an exact match, partial match, or no match. Although several lookup engines can return a partial match, an exact match preferably occurs in only one lookup engine. The comparison, validation, and transmission steps are repeated by each downstream lookup engine, with the lookup engine at the bottom of the stack validating and returning a final result to the packet processor. The returned final result reflects a search result with the highest match quality.

Packet Processor With Multi-Level Policing Logic

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US Patent:
20020089929, Jul 11, 2002
Filed:
Jan 8, 2001
Appl. No.:
09/757361
Inventors:
Mathieu Tallegas - Spokane WA, US
Kelly Fromm - Verdale WA, US
Dennis Paul - Liberty Lake WA, US
International Classification:
H04J003/14
H04L012/56
US Classification:
370/230000, 370/395210
Abstract:
A switch includes a backplane and multiple packet processors. One or more packet processors include multi-level policing logic. The packet processor receives a packet and classifies the packet into multiple policeable groups. The packet is compared against bandwidth contracts defined for the policeable groups. Nested lookups are performed for the packet in a policing database to identify the multiple groups and to retrieve policing data for the multiple policeable groups. The policing results, which may be combined into a single policing result by taking the worst case policing result, are applied to disposition logic as recommendations, and are combined with other disposition recommendations to make a disposition decision for the packet.
Mathieu T Tallegas from Duvall, WA, age ~53 Get Report