Resumes
Resumes

Senior Design Engineer At Lattice Semiconductor
View pageLocation:
385 River Oaks Pkwy, San Jose, CA 95134
Industry:
Semiconductors
Work:
UCLA since Sep 2011
Graduate Student Researcher
Altera - San Jose, CA Jun 2012 - Sep 2012
IP Verification Intern
Marvell Semiconductor - Santa Clara, CA Jan 2007 - Sep 2011
Analog Engineer
Graduate Student Researcher
Altera - San Jose, CA Jun 2012 - Sep 2012
IP Verification Intern
Marvell Semiconductor - Santa Clara, CA Jan 2007 - Sep 2011
Analog Engineer
Education:
University of California, Los Angeles 2011 - 2012
MSEE, Analog/Mixed Signal Design University of California, Berkeley 2004 - 2006
Bachelor of Science (B.S.), Electrical Engineering and Computer Science Diablo Valley College
MSEE, Analog/Mixed Signal Design University of California, Berkeley 2004 - 2006
Bachelor of Science (B.S.), Electrical Engineering and Computer Science Diablo Valley College
Skills:
Analog
Analog Circuit Design
Debugging
Cadence Virtuoso
Embedded Systems
Verilog
Spice
Simulations
Cmos
Mixed Signal
Fpga
Circuit Design
Semiconductors
Ic
Vlsi
Eda
Modelsim
Integrated Circuit Design
Asic
Matlab
Cadence
Pll
Spectre
Signal Integrity
Power Integrity
Cadence Sigrity
Serdes
Design Engineering
Application Specific Integrated Circuits
Analog Circuit Design
Debugging
Cadence Virtuoso
Embedded Systems
Verilog
Spice
Simulations
Cmos
Mixed Signal
Fpga
Circuit Design
Semiconductors
Ic
Vlsi
Eda
Modelsim
Integrated Circuit Design
Asic
Matlab
Cadence
Pll
Spectre
Signal Integrity
Power Integrity
Cadence Sigrity
Serdes
Design Engineering
Application Specific Integrated Circuits
Languages:
English