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Marko Sokolich Phones & Addresses

  • 432 Denslow Ave, Los Angeles, CA 90049 (310) 397-6661 (310) 472-3183
  • Mammoth Lakes, CA
  • 432 Denslow Ave, Los Angeles, CA 90049

Work

Position: Self employed Professional/Technical

Education

Degree: Graduate or professional degree

Industries

Semiconductors

Resumes

Resumes

Marko Sokolich Photo 1

Marko Sokolich

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Location:
Greater Los Angeles Area
Industry:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Marko Sokolich
President
Sokolich Consulting, Inc
2120 Colorado Ave, Santa Monica, CA 90404

Publications

Us Patents

Photo Induced-Emf Sensor Shield

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US Patent:
7176542, Feb 13, 2007
Filed:
Apr 22, 2004
Appl. No.:
10/830540
Inventors:
Gilmore J. Dunning - Newbury Park CA,
Marko Sokolich - Los Angeles CA,
Deborah Vogel - Moorpark CA,
David M. Pepper - Malibu CA,
International Classification:
H01L 31/0232
US Classification:
257435, 257457, 257E27125
Abstract:
A photo-EMF detector including a shield to prevent a portion of the detector from illumination. The shield prevents the generation of unwanted noise-currents, thus increasing the performance of the photo-EMF detector.

Interconnect With High Aspect Ratio Plugged Vias

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US Patent:
7470619, Dec 30, 2008
Filed:
Dec 1, 2006
Appl. No.:
11/607494
Inventors:
Mary Y. Chen - Oak Park CA,
James Chingwei Li - Simi Valley CA,
Philip H. Lawyer - Thousand Oaks CA,
Marko Sokolich - Los Angeles CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/44
H01L 21/4763
US Classification:
438675, 438618, 438631, 438652, 438674, 438678, 257E23141, 257E21175, 257E21586
Abstract:
Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

Electronic Device With Reduced Interface Charge Between Epitaxially Grown Layers And A Method For Making The Same

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US Patent:
7531851, May 12, 2009
Filed:
Feb 28, 2007
Appl. No.:
11/713070
Inventors:
Rajesh D. Rajavel - Oak Park CA,
Mary Y. Chen - Oak Park CA,
Steven S. Bui - Simi Valley CA,
David H. Chow - Newbury Park CA,
James Chingwei Li - Simi Valley CA,
Mehran Mokhtari - Thousand Oaks CA,
Marko Sokolich - Los Angeles CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 31/0328
US Classification:
257197, 257592, 257E27053, 438312, 438341, 438357
Abstract:
An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Group Iii-V Compound Semiconductor Based Heterojuncton Bipolar Transistors With Various Collector Profiles On A Common Wafer

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US Patent:
7576409, Aug 18, 2009
Filed:
Aug 10, 2005
Appl. No.:
11/202001
Inventors:
Mary Chen - Oak Park CA,
Marko Sokolich - Los Angeles CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 31/0328
US Classification:
257560, 257197, 257566, 257563, 257564
Abstract:
A wafer comprising at least one high FHBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.

Electronic Device With Reduced Interface Charge Between Epitaxially Grown Layers And A Method For Making The Same

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US Patent:
7582536, Sep 1, 2009
Filed:
Aug 14, 2008
Appl. No.:
12/191482
Inventors:
Rajesh D. Rajavel - Oak Park CA,
Mary Y. Chen - Oak Park CA,
Steven S. Bui - Simi Valley CA,
David H. Chow - Newbury Park CA,
James Chingwei Li - Simi Valley CA,
Mehran Mokhtari - Thousand Oaks CA,
Marko Sokolich - Los Angeles CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/331
H01L 21/8222
US Classification:
438312, 438341, 438357, 438906, 257197, 257592, 257E27053, 257E21108, 257E21226
Abstract:
An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Inp Based Heterojunction Bipolar Transistors With Emitter-Up And Emitter-Down Profiles On A Common Wafer

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US Patent:
7655529, Feb 2, 2010
Filed:
Feb 7, 2005
Appl. No.:
11/052935
Inventors:
Mary Chen - Oak Park CA,
Marko Sokolich - Los Angeles CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/331
US Classification:
438312, 257E21387
Abstract:
A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Modulation Doped Super-Lattice Sub-Collector For High-Performance Hbts And Bjts

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US Patent:
7868335, Jan 11, 2011
Filed:
Aug 18, 2008
Appl. No.:
12/193436
Inventors:
James Chingwei Li - Simi Valley CA,
Marko Sokolich - Los Angeles CA,
Tahir Hussain - Calabasas CA,
David H. Chow - Newbury Park CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 21/20
US Classification:
257 79, 257 94, 257103, 257194, 257198, 257201, 257E21125, 257E21127, 257E21603, 257E27012, 257E27128, 257E29022, 257E29066, 257E29114, 257E29189, 257E31073, 438207, 438268, 438302, 438309, 438319
Abstract:
A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.

Modulation Doped Super-Lattice Base For Heterojunction Bipolar Transistors

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US Patent:
8178946, May 15, 2012
Filed:
Nov 20, 2009
Appl. No.:
12/623325
Inventors:
James Chingwei Li - Simi Valley CA,
Marko Sokolich - Los Angeles CA,
Tahir Hussain - Calabasas CA,
David H. Chow - Newbury Park CA,
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 29/00
US Classification:
257552, 257 26, 257558, 257559, 257561, 257E29033
Abstract:
A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.
Marko Sokolich from Los Angeles, CA, age ~63 Get Report