Inventors:
Mark D. Noll - Santa Clara CA
Kenneth E. Scott - Sherwood OR
Robert L. Walker - Boulder CO
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 9455
H01L 2170
Abstract:
A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i. e. represent a proper subset of, the plurality of circuit elements of the circuit configuration; means for identifying a most critical path through each of the specified circuit elements based upon the static timing information, whereby preferably the most critical path is that path having the least slack defined as the difference between a required time at which a signal should reach the specified circuit element and an arrival time at which the signal is expected to reach the specified circuit element; and means for generating layout constraints from the most critical path through each of the specified circuit elements, whereby at least one constraint is generated covering each of the specified circuit elements. Also disclosed is a feature whereby any paths that do no meet specified filter criteria, and paths that are duplicates of others, are discarded, thereby retaining only irredudant critical paths on which to base layout constraints.