Search

Mark Chadurjian Phones & Addresses

  • Burlington, VT
  • 35 Corduroy Rd, Essex Jct, VT 05452 (802) 878-5519
  • Essex Junction, VT
  • Mount Rainier, MD
  • 2 Harbor Watch Rd, Burlington, VT 05401 (802) 878-5519

Work

Company: Clearpath ip law pllc Dec 2015 Position: Registered patent attorney

Education

Degree: Doctor of Jurisprudence, Doctorates School / High School: The Catholic University of America 1980 to 1984

Skills

Project Management • Program Management • Business Strategy • Customer Service • Cloud Computing • System Administration • Microsoft Excel • Change Management • Team Leadership • Patents • Intellectual Property • Contract Negotiation • Mergers • Patent Litigation • Software Licensing • Strategy • Client Services • Due Diligence • Licensing Agreements • Mergers and Acquisitions • Licensing • Patentability • Copyright Law • Open Source Software • Open Source Licensing • Patent Law

Ranks

Licence: Maryland - Active Date: 1985

Industries

Information Technology And Services

Professional Records

Lawyers & Attorneys

Mark Chadurjian Photo 1

Mark Frank Chadurjian, Burlington VT - Lawyer

View page
Address:
2 Harbor Watch Rd, Burlington, VT 05401
(802) 310-2399 (Office)
Licenses:
Maryland - Active 1985
Mark Chadurjian Photo 2

Mark Chadurjian, Essex Junction VT - Lawyer

View page
Office:
IBM Corp.
1000 River St., P.o. Box 915/972-2, Essex Junction, VT
Responsibilities:
Intellectual Property(100%)
ISLN:
908456428
Admitted:
1985
University:
Union College - Schenectady, NY, B.S.E.E.
Law School:
Catholic University of America, J.D.

Resumes

Resumes

Mark Chadurjian Photo 3

Registered Patent Attorney

View page
Location:
199 Main St, Burlington, VT 05401
Industry:
Information Technology And Services
Work:
Clearpath Ip Law Pllc
Registered Patent Attorney

Downs Rachlin Martin Pllc May 2014 - Nov 2015
Of Counsel, Ip Practice Group

Ibm 2003 - Mar 2014
Senior Counsel Iplaw

Ibm 1993 - 2003
Iplaw Counsel

Ibm 1985 - 1993
Senior Attorney
Education:
The Catholic University of America 1980 - 1984
Doctor of Jurisprudence, Doctorates
Union College 1976 - 1980
Bachelors, Bachelor of Science, Electronics Engineering, Electronics
Skills:
Project Management
Program Management
Business Strategy
Customer Service
Cloud Computing
System Administration
Microsoft Excel
Change Management
Team Leadership
Patents
Intellectual Property
Contract Negotiation
Mergers
Patent Litigation
Software Licensing
Strategy
Client Services
Due Diligence
Licensing Agreements
Mergers and Acquisitions
Licensing
Patentability
Copyright Law
Open Source Software
Open Source Licensing
Patent Law

Publications

Us Patents

Solder Mass Having Conductive Encapsulating Arrangement

View page
US Patent:
51307790, Jul 14, 1992
Filed:
Jun 19, 1990
Appl. No.:
7/540256
Inventors:
Birendra N. Agarwala - Hopewell Junction NY
Aziz M. Ahsan - Hopewell Junction NY
Arthur Bross - Poughkeepsie NY
Mark F. Chadurjian - Essex Junction VT
Nicholas G. Koopman - Hopewell Junction NY
Li-Chung Lee - Saratoga CA
Karl J. Puttlitz - Wappingers Falls NY
Sudipta K. Ray - Wappingers Falls NY
James G. Ryan - Essex Junction VT
Joseph G. Schaefer - Berkshire NY
Kamalesh K. Srivastava - Wappingers Falls NY
Paul A. Totta - Poughkeepsie NY
Erick G. Walton - South Burlington VT
Adolf E. Wirsing - South Hero VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
H01L 2350
H01L 2354
US Classification:
357 67
Abstract:
The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Method Of Forming Dual Height Solder Interconnections

View page
US Patent:
52518060, Oct 12, 1993
Filed:
Apr 16, 1992
Appl. No.:
7/870647
Inventors:
Birendra N. Agarwala - Hopewell Junction NY
Aziz M. Ahsan - Hopewell Junction NY
Arthur Bross - Poughkeepsie NY
Mark F. Chadurjian - Essex Junction VT
Nicholas G. Koopman - Hopewell Junction NY
Li-Chung Lee - Saratoga CA
Karl J. Puttlitz - Wappingers Falls NY
Sudipta K. Ray - Wappingers Falls NY
James G. Ryan - Essex Junction VT
Joseph G. Schaefer - Berkshire NY
Kamalesh K. Srivastava - Wappingers Falls NY
Paul A. Totta - Poughkeepsie NY
Erick G. Walton - South Burlington VT
Adolf E. Wirsing - South Hero VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21283
US Classification:
22818022
Abstract:
The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
Mark F Chadurjian from Burlington, VT, age ~67 Get Report