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Mark Joseph Buxton

from Oceanside, CA
Age ~47
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Also known as:
Mark J Buxton, Mark Mark Buxton, Markjoseph Buxton
Related to:
Mary Suzanne Buxton, 66Thomthy BuxtonValerie R Buxton, 57Michelle F Buxton, 48Paul Andrew Buxton, 50Shelly L Reed, 47Marvin L Buxton, 92Mitchell A Reed, 70Vincent R Buxton, 53Kim A Reed, 67
Connected to:
Ashley N Buxton, 41Barbara E Buxton, 73Bradley V Buxton, 59Buchanan Buxton, 72Bud L Buxton, 71Catrina L Buxton, 37Clifford S Buxton, 70Dale R Buxton, 62Danny R Buxton, 72Darby Buxton, 33

Mark Buxton Phones & Addresses

  • Oceanside, CA
  • 1893 Monterey Dr, Livermore, CA 94551 (925) 373-0571
  • 322 13Th St, Huntingtn Bch, CA 92648 (714) 849-2848
  • 119 11Th St APT 3, Huntingtn Bch, CA 92648
  • Huntington Beach, CA
  • San Marcos, CA

Professional Records

Lawyers & Attorneys

Mark Buxton Photo 1

Mark Buxton - Lawyer

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ISLN:
911335895
Admitted:
1993

Resumes

Resumes

Mark Buxton Photo 2

Mark Buxton

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mark Buxton
President
EYECAST DESIGNS, INC
119 11 St #3, Huntington Beach, CA 92648
Mark Buxton
President, President
LAZY "B" RANCH-GUARDIAN DOGS, INC
3640 Butters Dr, Oakland, CA 94602

Publications

Us Patents

Method And Apparatus For Performing Horizontal Addition And Subtraction

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US Patent:
7395302, Jul 1, 2008
Filed:
Jun 30, 2003
Appl. No.:
10/610784
Inventors:
William W. Macy - Palo Alto CA, US
Eric Debes - Santa Clara CA, US
Mark J. Buxton - Chandler AZ, US
Patrice Roussel - Portland OR, US
Julien Sebot - Hillsboro OR, US
Huy V. Nguyen - Pflugerville TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/50
US Classification:
708670, 712221
Abstract:
A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.

Gathering And Scattering Multiple Data Elements

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US Patent:
8447962, May 21, 2013
Filed:
Dec 22, 2009
Appl. No.:
12/644440
Inventors:
Christopher J. Hughes - Cupertino CA, US
Mayank Bomb - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Mark J. Buxton - Chandler AZ, US
Mark J. Charney - Lexington MA, US
Srinivas Chennupaty - Portland OR, US
Jesus Corbal - Barcelona, ES
Martin G. Dixon - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki (Saito) Ido - Sunnyvale CA, US
Peter Lachner - Heroldstatt, DE
Gilbert Neiger - Portland OR, US
Chris J. Newburn - South Beloit IL, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Bret L. Toll - Hillsboro OR, US
Robert Valentine - Kiryat Tivon, IL
Jeffrey G. Wiedemeier - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00
US Classification:
712244
Abstract:
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Instruction And Logic For Performing A Dot-Product Operation

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US Patent:
20080071851, Mar 20, 2008
Filed:
Sep 20, 2006
Appl. No.:
11/524852
Inventors:
Ronen Zohar - Sunnyvale CA, US
Mark Seconi - Beaverton OR, US
Rajesh Parthasarathy - Hillsboro OR, US
Srinivas Chennupaty - Portland OR, US
Mark Buxton - Chandler AZ, US
Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 7/52
US Classification:
708626
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Instruction And Logic For Performing A Dot-Product Operation

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US Patent:
20130290392, Oct 31, 2013
Filed:
Mar 15, 2013
Appl. No.:
13/844366
Inventors:
Ronen Zohar - Sunnyvale CA, US
Mark Seconi - Beaverton OR, US
Rajesh Parthasarathy - Hillsboro OR, US
Srinivas Chennupaty - Portland OR, US
Mark Buxton - Chandler AZ, US
Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 7/48
US Classification:
708490
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Instruction And Logic For Performing A Dot-Product Operation

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US Patent:
20140032624, Jan 30, 2014
Filed:
Sep 30, 2013
Appl. No.:
14/042681
Inventors:
Ronen Zohar - Sunnyvale CA, US
Mark Seconi - Beaverton OR, US
Rajesh Parthasarathy - Hillsboro OR, US
Srinivas Chennupaty - Portland OR, US
Mark Buxton - Chandler AZ, US
Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 17/10
US Classification:
708495
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Instruction And Logic For Performing A Dot-Product Operation

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US Patent:
20140032881, Jan 30, 2014
Filed:
Sep 30, 2013
Appl. No.:
14/042696
Inventors:
Ronen Zohar - Sunnyvale CA, US
Mark Seconi - Beaverton OR, US
Rajesh Parthasarathy - Hillsboro OR, US
Srinivas Chennupaty - Portland OR, US
Mark Buxton - Chandler AZ, US
Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 9/30
US Classification:
712207
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Method And Apparatus For Performing Logical Compare Operations

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US Patent:
20190286444, Sep 19, 2019
Filed:
Nov 8, 2018
Appl. No.:
16/184994
Inventors:
- Santa Clara CA, US
Ronen ZOHAR - Sunnyvale CA, US
Mark J. BUXTON - Chandler AZ, US
Zeev SPERBER - Zichron Yaakov, IL
Koby GOTTLIEB - Kiryat Tivon, IL
International Classification:
G06F 9/30
G06F 9/38
Abstract:
A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Method And Apparatus For Performing Logical Compare Operations

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US Patent:
20190087183, Mar 21, 2019
Filed:
Oct 18, 2018
Appl. No.:
16/164736
Inventors:
- Santa Clara CA, US
Ronen ZOHAR - Sunnyvale CA, US
Mark J. BUXTON - Chandler AZ, US
Zeev SPERBER - Zichron Yaakov, IL
Koby GOTTLIEB - Kiryat Tivon, IL
International Classification:
G06F 9/30
G06F 7/02
G06F 9/38
Abstract:
A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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Mark Joseph Buxton from Oceanside, CA, age ~47 Get Report