Search

Mark J Bohr

from Cary, NC
Age ~41
Get Report
Also known as:
Mark J Buhr, Mark Joseph Buhr, Joe Buhr
Related to:
Taylor Miles, 34Francis BuhrLori A Alarcon, 49Mark BuhrAndrea Dixon, 44
Connected to:
Amanda J Bohr, 42Hannah Bohr, 31Heather L Bohr, 47Janet M Bohr, 71Sharon A Bohr, 64Terry L Bohr, 60Digvijay Bohra, 54Jayshree Bohra, 45Kamlesh Bohra, 36Manish O Bohra, 47

Mark Bohr Phones & Addresses

  • Cary, NC
  • Safford, AZ
  • Chandler, AZ
  • Phoenix, AZ
  • Gilbert, AZ
  • Mesa, AZ
  • Thatcher, AZ
  • North Logan, UT
  • Park City, UT
  • Lakeside, AZ
  • Big Bear City, CA

Publications

Us Patents

Silicon Interposer-Based Hybrid Voltage Regulator System For Vlsi Devices

View page
US Patent:
7952194, May 31, 2011
Filed:
Oct 26, 2001
Appl. No.:
10/016793
Inventors:
Raj Nair - Gilbert AZ, US
Johanna Swan - Scottsdale AZ, US
Bala Natarajan - Phoenix AZ, US
Mark Bohr - Aloha OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/34
US Classification:
257723, 361704
Abstract:
A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.

Package On Active Silicon Semiconductor Packages

View page
US Patent:
20210013188, Jan 14, 2021
Filed:
Sep 28, 2017
Appl. No.:
16/641922
Inventors:
- Santa Clara CA, US
Sanka Ganesan - Chandler AZ, US
DOUG INGERLY - Santa Clara CA, US
ROBERT SANKMAN - Phoenix AZ, US
MARK BOHR - Aloha OR, US
DEBENDRA MALLIK - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 25/10
H01L 25/065
H01L 25/00
Abstract:
Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

3D Integrated Circuit Package With Window Interposer

View page
US Patent:
20150332994, Nov 19, 2015
Filed:
Jul 29, 2015
Appl. No.:
14/813014
Inventors:
Debendra MALLIK - Chandler AZ, US
Ram S. VISWANATH - Phoenix AZ, US
Sriram SRINIVASAN - Chandler AZ, US
Mark T. BOHR - Aloha OR, US
Andrew W. YEOH - Portland OR, US
Sairam AGRAHARAM - Chandler AZ, US
International Classification:
H01L 23/498
H01L 25/065
Abstract:
3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

Die Package Architecture With Embedded Die And Simplified Redistribution Layer

View page
US Patent:
20150187608, Jul 2, 2015
Filed:
Dec 26, 2013
Appl. No.:
14/141343
Inventors:
Sanka GANESAN - Chandler AZ, US
Thorsten MEYER - Regensburg, DE
Robert L. SANKMAN - Phoenix AZ, US
Mark T. BOHR - Aloha OR, US
Frank ZUDOCK - Regensburg, DE
International Classification:
H01L 21/56
H01L 23/00
Abstract:
A die package architecture with an embedded die and simplified redistribution layer is described. In one example a method includes attaching a front side of a die to a temporary carrier panel applying a molding compound around the die and over the temporary carrier panel. Removing the temporary carrier, applying a metal routing layer over the front side of the die and the molding compound, and applying a connection array to the metal routing layer.

3D Integrated Circuit Package With Window Interposer

View page
US Patent:
20140191419, Jul 10, 2014
Filed:
Dec 22, 2011
Appl. No.:
13/995917
Inventors:
Debendra Mallik - Chandler AZ, US
Ram S. Viswanath - Phoenix AZ, US
Sriram Srinivasan - Chandler AZ, US
Mark T. Bohr - Aloha OR, US
Andrew W. Yeoh - Portland OR, US
Sairam Agraharam - Chandler AZ, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 25/065
H01L 23/498
US Classification:
257777
Abstract:
3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
Control profile
Mark J Bohr from Cary, NC, age ~41 Get Report