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Margaret S Fyfield

from Portland, OR
Age ~71
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Also known as:
Margie S Fyfield, Margie Sanina Fyfield, Maragret S Fyfield, Margie I Malloy, Margaret D
Phone and address:
3006 Gladstone St, Portland, OR 97202
(503) 234-6814
Related to:
Janet F Fennell, 61Merwin ForbesThomas W Mcalexander, 35Cary Mcalexander, 51Donna Frankland, 65Evelyn Holloway, 68
Connected to:
Nancy G Fyhr, 75Nancy E Fykes, 53Carissa Fyksen, 48Denise T Fyksen, 40Jill H Fyksen, 77Amy C Fylan, 63Cindy A Fyle, 66Thomas R Fyle, 74Benjamin T Fyler, 35Jerry M Fyler, 81

Margaret Fyfield Phones & Addresses

  • 3006 Gladstone St, Portland, OR 97202 (503) 234-6814

Publications

Us Patents

Probing Fixture For Semiconductor Wafer

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US Patent:
7053639, May 30, 2006
Filed:
May 18, 2005
Appl. No.:
11/131885
Inventors:
Margaret S. Fyfield - Portland OR, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R 31/02
US Classification:
324754
Abstract:
A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.

Method For Probing A Semiconductor Wafer

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US Patent:
6927079, Aug 9, 2005
Filed:
Dec 6, 2000
Appl. No.:
09/731596
Inventors:
Margaret S. Fyfield - Portland OR, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L021/66
US Classification:
438 14, 438 18, 438 24, 438 11, 438 15
Abstract:
A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.
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Margaret S Fyfield from Portland, OR, age ~71 Get Report