Marco Zanuso

20220190833, Jun 16, 2022

Dec 10, 2020

17/117240

- San Diego CA, US
Giovanni MARUCCI - San Diego CA, US
Dongmin PARK - San Diego CA, US
Marco ZANUSO - Encinitas CA, US
Yiwu TANG - San Diego CA, US

H03L 7/093
H03K 3/037
H03M 3/00

A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

20210409007, Dec 30, 2021

Jun 29, 2021

17/362509

- San Diego CA, US
Marco Zanuso - Encinitas CA, US
Razak Hossain - San Diego CA, US
Hasnain Lakdawala - San Diego CA, US

H03K 3/017
H03L 7/093

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

20210409029, Dec 30, 2021

Jun 24, 2021

17/357478

- San Diego CA, US
Marco Zanuso - Encinitas CA, US
Razak Hossain - San Diego CA, US
Hasnain Lakdawala - San Diego CA, US

H03L 7/099
H03L 7/091
H03L 7/081
H03L 7/18

An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

20210072778, Mar 11, 2021

Sep 5, 2019

16/561839

- San Diego CA, US
Marco ZANUSO - Encinitas CA, US
Rajagopalan RANGARAJAN - San Diego CA, US
Yiwu TANG - San Diego CA, US

G05F 1/575
G05F 1/595
H03F 3/45

Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

20210044253, Feb 11, 2021

Oct 22, 2020

17/076998

- SAN DIEGO CA, US
Yinghan WANG - San Diego CA, US
Marco ZANUSO - Encinitas CA, US
Rajagopalan RANGARAJAN - San Diego CA, US

H03B 5/12
H03L 7/093
H03L 7/08

A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

20200091866, Mar 19, 2020

Sep 17, 2018

16/132731

- San Diego CA, US
Yinghan WANG - San Diego CA, US
Marco ZANUSO - Encinitas CA, US
Rajagopalan RANGARAJAN - San Diego CA, US

H03B 5/12
H03L 7/093

A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

20190326915, Oct 24, 2019

Apr 19, 2018

15/957441

- San Diego CA, US
Mehran Mohammadi Izad - San Diego CA, US
Marco Zanuso - Encinitas CA, US

H03L 7/089
H03L 7/099

An apparatus is disclosed that implements a sampling phase-locked loop. In an example aspect, the apparatus includes a phase frequency detector, a relative phase signal determiner, a voltage-controlled oscillator (VCO), and a feedback path. The phase frequency detector is configured to produce a phase indication signal based on a reference signal and a feedback signal. The relative phase signal determiner is coupled to the phase frequency detector and includes a sampler. The relative phase signal determiner is configured to determine a relative phase signal based on the phase indication signal using the sampler. The VCO is coupled to the relative phase signal determiner and is configured to produce an oscillating signal based on the relative phase signal. The feedback path is disposed between the VCO and the phase frequency detector. The feedback path is configured to provide the feedback signal to the phase frequency detector using the oscillating signal.

20160065195, Mar 3, 2016

Aug 28, 2014

14/471530

- San Diego CA, US
Serkan SAYILIR - Bingol, TR
Marco ZANUSO - San Diego CA, US
Yiwu TANG - San Diego CA, US

H03K 5/15
H03H 11/22
H03H 11/20

Certain aspects of the present disclosure provide methods and apparatus for generating multiple oscillating signals having different phases. One example multiphase generating circuit generally includes a first phase shifting circuit configured to phase shift an input signal having an input frequency, such that an output signal of the first phase shifting circuit has a first phase difference with respect to the input signal; a first frequency dividing circuit configured to receive the input signal and output a first set of signals having a first frequency less than the input frequency of the input signal; and a second frequency dividing circuit configured to receive the output signal of the first phase shifting circuit and output a second set of signals having a second frequency less than the input frequency of the input signal. The multiphase signals may be used for fast frequency estimation of the input signal or in N-path filters.