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Marc K Chason

from Schaumburg, IL
Age ~73
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Also known as:
Marc Christine Chason
Phone and address:
1809 Fairhaven Ln, Schaumburg, IL 60194
(847) 882-0982
Related to:
Davis Loudenslager Austin, 47Austin D Loudenslager, 47Michael E Vianzon, 45Jeffrey C Faulkner, 46Christine D Chason, 73Jeffrey C Faulkner, 81
Connected to:
Gary W Chason, 82Gregory L Chason, 32James Chason, 72Jesse Chason, 35Linda R Chason, 70Michael L Chason, 45Paul F Chason, 55Georgios C Chasparis, 46Dia Chass, 113Jacob Chass, 99

Marc Chason Phones & Addresses

  • 1809 Fairhaven Ln, Schaumburg, IL 60194 (847) 882-0982
  • Downers Grove, IL
  • Woodstock, IL
  • Westmont, IL
  • Clarendon Hills, IL
  • 1809 Fairhaven Ln, Schaumburg, IL 60194 (815) 212-2795

Work

Company: Marc chason and associates, inc May 2007 Position: President

Education

Degree: MS School / High School: State University of New York at Stony Brook 1973 to 1974 Specialities: Materials Science

Skills

Performance • Solutions • Sap • Management Consulting

Emails

m***c@ptd.net

Industries

Management Consulting

Resumes

Resumes

Marc Chason Photo 1

President

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Location:
Chicago, IL
Industry:
Management Consulting
Work:
Marc Chason and Associates, Inc since May 2007
President
Quantum Solar Group Sep 2008 - Oct 2009
Founding Partner
Motorola 2000 - 2007
Director, Motorola Labs, Physical Realization Research Center
Motorola Labs, Motorola 1983 - 2007
Motorola
Motorola 1983 - 2001
Director
Education:
State University of New York at Stony Brook 1973 - 1974
MS, Materials Science State University of New York at Stony Brook 1969 - 1973
BE, Engineering Science
Skills:
Performance
Solutions
Sap
Management Consulting

Business Records

Name / Title
Company / Classification
Phones & Addresses
Marc Chason
President
Marc Chason and Associates, Inc
Services-Misc
1809 Fairhaven Ln, Schaumburg, IL 60194

Publications

Us Patents

Structure And Method For Fabricating An Electro-Rheological Lens

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US Patent:
6585424, Jul 1, 2003
Filed:
Jul 25, 2001
Appl. No.:
09/911472
Inventors:
Marc Chason - Schaumburg IL
Daniel Gamota - Palatine IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G02B 636
US Classification:
385 88, 385 92, 385 93, 385 94, 438 29, 438 22, 438 31
Abstract:
High quality epitaxial layers of monocrystalline materials can be grown layered monocrystallinfe substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Formation of a compliant substrate may include utilizing surfactant-enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The layered monocrystalline substrates allow for the fabrication of at least one optical device with an insulating material laid over it, wherein the insulating material provides an optical aperture for use with the optical device. A conductive material can be deposited within the insulating material, and an electro-rheological lens can be inserted within the insulating material aperture, while being in contact with the conductive material.

Micro-Electro Mechanical System

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US Patent:
6649852, Nov 18, 2003
Filed:
Aug 14, 2001
Appl. No.:
09/929750
Inventors:
Marc Chason - Schaumburg IL
Andrew Skipor - West Chicago IL
Aroon Tungare - Winfield IL
Daniel Gamota - Palatine IL
Sanjar Ghaem - Chesapeak VA
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01H 3900
US Classification:
200181, 333262
Abstract:
The organic MEMS according to the present invention comprises a polymeric substrate comprising a substrate surface including a first region and a second region. A polymer coating is applied to the first region to provide a coating surface that is spaced apart from the substrate surface. A terminal is disposed on the second region. A metallic trace is affixed to the coating surface such that the metallic trace forms a flexible extension over the second region. The extension has a rest position where the extension is spaced apart from the terminal, and a flexed position where the extension is disposed towards the terminal. An actuator is used to provide an electric field to deflect the extension from the rest position to the flexed position. By changing the spacing between the extension and the terminal, it is possible to change the electrical condition provided by the MEMS.

Thinned Semiconductor Wafer And Die And Corresponding Method

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US Patent:
6780733, Aug 24, 2004
Filed:
Sep 6, 2002
Appl. No.:
10/236619
Inventors:
Marc Chason - Schaumburg IL
Paul Brazis - South Elgin IL
Krishna Kalyanasundaram - Chicago IL
Daniel Gamota - Palatine IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21301
US Classification:
438464, 438455, 438458
Abstract:
A wafer ( ) having integrated circuit elements formed therein is thinned and a first carrier ( ) is adhered thereto. The first carrier ( ) facilitates handling of the thinned wafer ( ). A second carrier ( ) is then adhered as well and the various integrated circuits are singulated to yield a plurality of thinned die ( ). Once the thinned die is mounted to a desired substrate ( ), the first carrier ( ) is readily removed. In one embodiment, the first carrier ( ) has an adhesive that becomes less adherent when exposed to a predetermined stimulus (such as a given temperature range or a given frequency range of photonic energy). Such thinned die (or modules containing such die) are readily amenable to stacking in order to achieve significantly increased circuit densities.

Heater For Temperature Control Integrated In Circuit Board And Method Of Manufacture

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US Patent:
6781056, Aug 24, 2004
Filed:
Feb 28, 2003
Appl. No.:
10/376858
Inventors:
Shawn ORourke - Tempe AZ
Daniel J. Sadler - Gilbert AZ
Marc K. Chason - Schaumburg IL
Manes Eliacin - Buffalo Grove IL
Claudia V. Gamboa - Chicago IL
Robert Terbrueggen - Manhattan Beach CA
Ke K. Lian - Palatine IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H05K 103
US Classification:
174 524, 174255, 174256, 174260, 338314
Abstract:
Circuit boards ( ) and methods for fabricating circuit boards that include heaters for maintaining temperature sensitive components at an operating temperature are provided. Resistive traces ( ) are included in the circuit boards proximate temperature sensitive apparatus ( ). Thermally conductive patches ( ) are interposed between the resistive traces and the temperature sensitive components. The thermally conductive patches establish zones of relatively uniform temperatures. According to a preferred embodiment of the invention the temperature sensitive apparatus comprises a fluid conduit ( ).

Selective Underfill For Flip Chips And Flip-Chip Assemblies

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US Patent:
6800946, Oct 5, 2004
Filed:
Dec 23, 2002
Appl. No.:
10/328326
Inventors:
Marc Chason - Schaumburg IL
Jan Danvir - Arlington Heights IL
Assignee:
Motorola, Inc - Arlington Heights IL
International Classification:
H01L 310203
US Classification:
257778, 257100, 257416, 257433, 257787, 438 25, 438 26, 438 51, 438 64, 438108, 438126, 29841
Abstract:
The invention provides a method for attaching a flip chip to a printed wiring board. A bumped opto-electronic or electromechanical flip chip is provided. An underfill material is applied to a first portion of the flip chip, wherein a second portion of the flip chip is free of the underfill material. The flip chip is positioned on a printed wiring board, and a bumped portion of the flip chip is heated to electrically connect the flip chip to the printed wiring board. The second portion of the flip chip remains free of the underfill material when the flip chip is electrically connected to the printed wiring board.

Structure And Method For Fabricating Semiconductor Structures And Devices For Detecting An Object

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US Patent:
7161227, Jan 9, 2007
Filed:
Jun 29, 2004
Appl. No.:
10/878414
Inventors:
Robert Lempkowski - Elk Grove IL, US
Marc Chason - Schaumburg IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 29/00
US Classification:
257531, 257684, 257528, 257428, 257E27001, 257E21022, 257E2704
Abstract:
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A high quality layer of compound semiconductor material is used to form a source component and a receiver component that are interconnected with an antenna and each other within a semiconductor structure that can detect a parameter, such as the speed, of an object.

Method And Apparatus To Aide In Emergency Egress

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US Patent:
7199724, Apr 3, 2007
Filed:
May 17, 2005
Appl. No.:
11/130648
Inventors:
Janice M. Danvir - Arlington Heights IL, US
Marc K. Chason - Schaumburg IL, US
Katherine M. Devanie - Arlington Heights IL, US
David A. Hume - Deer Park IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G08B 3/00
G08B 5/00
G08B 7/00
US Classification:
3406911, 340540, 340577, 340628
Abstract:
A method and apparatus are provided to aide in emergency egress of a structure. More particularly, egress indicators are co-located with hazard sensors. During detection of a hazard condition, locations of sensors detecting the hazard are identified and a pathway directing traffic away from the hazard is determined. Finally, the egress indicators are operated to direct traffic down the determined pathway.

Electronic Module Interconnection Apparatus

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US Patent:
7492604, Feb 17, 2009
Filed:
Apr 21, 2006
Appl. No.:
11/379751
Inventors:
Paul W. Brazis - South Elgin IL, US
Marc K. Chason - Schaumburg IL, US
Daniel R. Gamota - Palatine IL, US
Krishna Kalyanasundaram - Elmhurst IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H05K 1/11
US Classification:
361784, 361737
Abstract:
An electronic apparatus, includes a plurality of electronic modules, each having a maximum thickness of no more than 90 microns, each comprising a substrate having a two sided edge connection pattern. The electronic modules are arranged adjacent to each other. Each pad of a first set of connection pads on a first electronic module is conductively connected to an opposing pad of a second set of connection pads of a second electronic module. The first set of connection pads is separated from the second set of connection pads by electrically conductive material that is less than 15 microns thick.
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Marc K Chason from Schaumburg, IL, age ~73 Get Report