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Mamata A Patnaik

from Wake Forest, NC
Age ~66
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Also known as:
Marmata Patnaik, Mamata A Patniak, Mamata Patnalk, Mamata Patroi, Mamata K
Phone and address:
401 Cottesbrook Dr, Wake Forest, NC 27587
Related to:
Shyama PatnaikAmiya K Patnaik, 94Asis K Patnaik, 62Asit K Patnaik, 59Tammy M Inghram, 60Asit Patnaik
Connected to:
Alok Patnaik, 40Anjela Patnaik, 53Aradhana R Patnaik, 49Ashish K Patnaik, 49Divya Patnaik, 38Goutam Patnaik, 40Jayanti Patnaik, 71Madhusmita Patnaik, 48Natasha Patnaik, 33Pradipta Patnaik, 56

Mamata Patnaik Phones & Addresses

  • 401 Cottesbrook Dr, Wake Forest, NC 27587
  • 399 Division St, Clermont, FL 34711
  • San Jose, CA
  • 2752 Windsor Hill Dr, Windermere, FL 34786
  • Robesonia, PA
  • West Lawn, PA
  • 335 Elan Village Ln UNIT 207, San Jose, CA 95134

Work

Company: Qualcomm Jan 2011 to Feb 2015 Position: Senior staff engineer

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: Suny Stony Brook 1976 to 1980

Skills

Microsoft Excel • Microsoft Word • Management • English • Powerpoint • Outlook • Leadership • C++ • Windows • Process Improvement • Research • C • Microsoft Office • Customer Service • Electronics • Soc • Embedded Systems • Debugging • Semiconductors • Testing • Analog • Asic • Ic • Wireless • Engineering Management • Semiconductor Industry

Industries

Semiconductors

Resumes

Resumes

Mamata Patnaik Photo 1

Mamata Patnaik

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Location:
Wake Forest, NC
Industry:
Semiconductors
Work:
Qualcomm Jan 2011 - Feb 2015
Senior Staff Engineer
Intellon Corporation May 2005 - Jan 2011
Principal Product Engineer
Agere/Lucent/Cirent Semiconductor Jan 1996 - May 2005
Senior Member of Technical Staff
Education:
Suny Stony Brook 1976 - 1980
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Microsoft Excel
Microsoft Word
Management
English
Powerpoint
Outlook
Leadership
C++
Windows
Process Improvement
Research
C
Microsoft Office
Customer Service
Electronics
Soc
Embedded Systems
Debugging
Semiconductors
Testing
Analog
Asic
Ic
Wireless
Engineering Management
Semiconductor Industry

Publications

Us Patents

Process To Integrate Fabrication Of Bipolar Devices Into A Cmos Process Flow

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US Patent:
20070069295, Mar 29, 2007
Filed:
Sep 28, 2005
Appl. No.:
11/237634
Inventors:
Daniel Kerr - Orlando FL, US
Mamata Patnaik - Windermere FL, US
Mario Pita - Harmony FL, US
Venkat Raghavan - Union City CA, US
Alan Chen - Windermere FL, US
International Classification:
H01L 21/8238
H01L 21/8249
H01L 27/12
US Classification:
257351000, 438202000, 438234000, 257E21269
Abstract:
A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Process To Integrate Fabrication Of Bipolar Devices Into A Cmos Process Flow

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US Patent:
20070161173, Jul 12, 2007
Filed:
Dec 15, 2006
Appl. No.:
11/639847
Inventors:
Daniel Kerr - Orlando FL, US
Mamata Patnaik - Windermere FL, US
Mario Pita - Harmony FL, US
Venkat Raghavan - Union City CA, US
Alan Chen - Windermere FL, US
International Classification:
H01L 21/8234
H01L 21/8238
H01L 21/8249
H01L 21/302
US Classification:
438197000, 438202000, 438203000, 438204000, 438207000, 438234000, 438236000, 438723000, 438726000, 438733000, 438743000, 257E27109
Abstract:
A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.
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Mamata A Patnaik from Wake Forest, NC, age ~66 Get Report