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Mamata A Patnaik

from Wake Forest, NC
Age ~64
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Also known as:
Mamata Patnaik, Marmata Patnaik, Mamata Patniak, Mamata Patnalk, Mamata K
Related to:
Shyama Patnaik, 50Amiya K Patnaik, 92Asis K Patnaik, 60Asit K Patnaik, 57Tammy M Inghram, 58Asit Patnaik
Connected to:
Alok Patnaik, 38Anjela Patnaik, 51Aradhana R Patnaik, 47Ashish K Patnaik, 47Divya Patnaik, 36Goutam Patnaik, 38Jayanti Patnaik, 69Madhusmita Patnaik, 46Natasha Patnaik, 31Pradipta Patnaik, 54

Mamata Patnaik Phones & Addresses

  • Wake Forest, NC
  • Clermont, FL
  • San Jose, CA
  • 2752 Windsor Hill Dr, Windermere, FL 34786
  • Robesonia, PA
  • West Lawn, PA
  • 335 Elan Village Ln UNIT 207, San Jose, CA 95134

Work

Company: Atheros communications Position: Principal product engineer

Education

Degree: Associate degree or higher

Industries

Semiconductors

Resumes

Resumes

Mamata Patnaik Photo 1

Principal Product Engineer At Atheros Communications

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Position:
Principal Product Engineer at Atheros Communications
Location:
Orlando, Florida Area
Industry:
Semiconductors
Work:
Atheros Communications
Principal Product Engineer

Publications

Us Patents

Process To Integrate Fabrication Of Bipolar Devices Into A Cmos Process Flow

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US Patent:
20070069295, Mar 29, 2007
Filed:
Sep 28, 2005
Appl. No.:
11/237634
Inventors:
Daniel Kerr - Orlando FL,
Mamata Patnaik - Windermere FL,
Mario Pita - Harmony FL,
Venkat Raghavan - Union City CA,
Alan Chen - Windermere FL,
International Classification:
H01L 21/8238
H01L 21/8249
H01L 27/12
US Classification:
257351000, 438202000, 438234000, 257E21269
Abstract:
A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

Process To Integrate Fabrication Of Bipolar Devices Into A Cmos Process Flow

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US Patent:
20070161173, Jul 12, 2007
Filed:
Dec 15, 2006
Appl. No.:
11/639847
Inventors:
Daniel Kerr - Orlando FL,
Mamata Patnaik - Windermere FL,
Mario Pita - Harmony FL,
Venkat Raghavan - Union City CA,
Alan Chen - Windermere FL,
International Classification:
H01L 21/8234
H01L 21/8238
H01L 21/8249
H01L 21/302
US Classification:
438197000, 438202000, 438203000, 438204000, 438207000, 438234000, 438236000, 438723000, 438726000, 438733000, 438743000, 257E27109
Abstract:
A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.
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Mamata A Patnaik from Wake Forest, NC, age ~64 Get Report