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Lucio Luigi Lanza

from Palo Alto, CA
Age ~80

Lucio Lanza Phones & Addresses

  • 972 Hamilton Ave, Palo Alto, CA 94301 (650) 619-2003
  • Mauston, WI
  • San Francisco, CA
  • Menlo Park, CA
  • San Jose, CA
  • Santa Clara, CA
  • 972 Hamilton Ave, Palo Alto, CA 94301

Industries

Semiconductors

Resumes

Resumes

Lucio Lanza Photo 1

Lucio Lanza

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Location:
San Francisco Bay Area
Industry:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Lucio Lanza
President
Lucio Lanza Inc
Business Services at Non-Commercial Site
15276 Karl Ave, Los Gatos, CA 95030
Lucio Lanza
Director
JASPER DESIGN AUTOMATION, INC
2655 Seely Ave, San Jose, CA 95134
707 California St, Mountain View, CA 94041
Lucio Lanza
Celebrity Life Travel, LLC
165 University Ave, Palo Alto, CA 94301
Lucio Lanza
Lanza Techventures Management I, LLC
Venture Capital Investment
165 University Ave, Palo Alto, CA 94301
Lucio Lanza
President
EDA SYSTEMS, INC
3255-3 Scott Blvd, Santa Clara, CA 95054
19981 Lannoy Ct, Saratoga, CA
Lucio Lanza
PRESIDIO MANAGEMENT GROUP V, LLC
Menlo Park, CA 94025

Publications

Us Patents

Method And Apparatus For Thermal Testing Of Semiconductor Chip Designs

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US Patent:
7191413, Mar 13, 2007
Filed:
Mar 11, 2005
Appl. No.:
11/078047
Inventors:
Rajit Chandra - Cupertino CA, US
Lucio Lanza - Palo Alto CA, US
Assignee:
Gradient Design Automation, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 6, 716 5
Abstract:
A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e. g. , to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e. g. , in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.

Method And Process For Design Of Integrated Circuits Using Regular Geometry Patterns To Obtain Geometrically Consistent Component Features

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US Patent:
7278118, Oct 2, 2007
Filed:
Nov 4, 2005
Appl. No.:
11/267569
Inventors:
Lawrence T. Pileggi - Pittsburgh PA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Lucio L. Lanza - Palo Alto CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 19
Abstract:
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Method And Process For Design Of Integrated Circuits Using Regular Geometry Patterns To Obtain Geometrically Consistent Component Features

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US Patent:
7906254, Mar 15, 2011
Filed:
Oct 2, 2007
Appl. No.:
11/906736
Inventors:
Lawrence T. Pileggi - Pittsburgh PA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Lucio L. Lanza - Palo Alto CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 19/00
G03F 1/00
US Classification:
430 5, 716 50, 716100, 700121
Abstract:
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Method And Process For Design Of Integrated Circuits Using Regular Geometry Patterns To Obtain Geometrically Consistent Component Features

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US Patent:
20100162193, Jun 24, 2010
Filed:
Jan 29, 2010
Appl. No.:
12/697161
Inventors:
Lawrence T. Pileggi - Pittsburgh PA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Lucio L. Lanza - Palo Alto CA, US
International Classification:
G06F 17/50
US Classification:
716 10, 716 17
Abstract:
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Systems And Methods For Obfuscating A Circuit Design

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US Patent:
20220277126, Sep 1, 2022
Filed:
May 16, 2022
Appl. No.:
17/745814
Inventors:
- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US
International Classification:
G06F 30/39
G06F 30/30
G06F 30/33
G06F 30/367
G06F 30/392
G06F 30/398
G06F 30/3323
H01L 23/00
Abstract:
Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

Systems And Methods For Obfuscating A Circuit Design

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US Patent:
20200285795, Sep 10, 2020
Filed:
May 20, 2020
Appl. No.:
16/879045
Inventors:
- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US
International Classification:
G06F 30/39
G06F 30/30
G06F 30/33
G06F 30/367
G06F 30/392
G06F 30/398
G06F 30/3323
H01L 23/00
Abstract:
Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

Methods For Engineering Integrated Circuit Design And Development

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US Patent:
20200089833, Mar 19, 2020
Filed:
Sep 25, 2019
Appl. No.:
16/583170
Inventors:
- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US
International Classification:
G06F 17/50
H01L 23/00
Abstract:
Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Systems And Methods For Obfuscating A Circuit Design

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US Patent:
20190392105, Dec 26, 2019
Filed:
Sep 9, 2019
Appl. No.:
16/564536
Inventors:
- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US
International Classification:
G06F 17/50
H01L 23/00
Abstract:
Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
Lucio Luigi Lanza from Palo Alto, CA, age ~80 Get Report