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Luciana U Meli

from Albany, NY
Age ~47
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Also known as:
Luciana M Thompson, Luciana Meli Thompson
Phone and address:
260 Woodscape Dr, Albany, NY 12203
Connected to:
Ali S Meli, 43Amanda Meli, 44Anna M Meli, 75Beatrice Meli, 106Blaise J Meli, 75Ellen M Meli, 71Eric B Meli, 50Jahna D Meli, 45Jennie Meli, 101Kelly J Meli, 66

Luciana Meli Phones & Addresses

  • 260 Woodscape Dr, Albany, NY 12203
  • Pleasant Valley, NY
  • Minneapolis, MN
  • 2441 Lancashire Dr, Ann Arbor, MI 48105 (734) 998-3514
  • 9617 Great Hills Trl, Austin, TX 78759 (512) 349-0798
  • 1003 26Th St, Austin, TX 78705 (512) 476-5057
  • 1908 San Antonio St, Austin, TX 78705 (512) 476-5057
  • 1919 Burton Dr, Austin, TX 78741 (512) 851-0093
  • 1003 W 26Th St, Austin, TX 78705 (512) 633-5562

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Luciana Meli Photo 1

Manager, Foundational Patterning

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Location:
Albany, NY
Industry:
Semiconductors
Work:
Ibm
Manager, Foundational Patterning
Ibm
Advisory Engineer
Rensselaer Polytechnic Institute Oct 2009 - Apr 2013
Research Scientist
University of Minnesota 2008 - 2009
Postdoctoral Associate
University of Michigan Oct 2005 - Dec 2007
Visiting Researcher
Education:
The University of Texas at Austin 2001 - 2007
Doctorates, Doctor of Philosophy, Chemical Engineering Universidad Nacional Autónoma De México 1996 - 2001
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Nanotechnology
Characterization
Spectroscopy
Materials Science
Matlab
Chemistry
Thin Films
Cell Culture
Powder X Ray Diffraction
Scanning Electron Microscopy
Chemical Engineering
Science
Design of Experiments
Mathematical Modeling
Research and Development
Luciana Meli Photo 2

Luciana Meli

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Publications

Us Patents

Lithography Process Delay Characterization And Effective Dose Compensation

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US Patent:
20210132502, May 6, 2021
Filed:
Nov 6, 2019
Appl. No.:
16/676334
Inventors:
- Armonk NY, US
Luciana Meli - Albany NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Cody John Murray - Scotia NY, US
International Classification:
G03F 7/26
G03F 7/20
Abstract:
Techniques for lithography process delay characterization and effective dose compensation are provided. In one aspect, a method of analyzing a lithography process includes: applying a photoresist to a wafer; performing a post-apply bake of the photoresist; patterning the photoresist with sequences of open frame base line exposures performed at doses of from about 92% E0 to about 98% E0, and ranges therebetween, at multiple fields of the wafer separated by intervening programmed delay intervals, wherein E0 is the photoresist dose-to-clear; performing a post-exposure bake of the photoresist; developing the photoresist; performing a full wafer inspection to generate a grayscale map of the wafer; and analyzing the grayscale map to determine whether the intervening programmed delay intervals had an effect on the open frame base line exposures during the lithography process. Exposure dose compensation can then be applied to maintain a constant effective dose.

Sequential Infiltration Synthesis Extreme Ultraviolet Single Expose Patterning

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US Patent:
20210082697, Mar 18, 2021
Filed:
Sep 13, 2019
Appl. No.:
16/570603
Inventors:
- Armonk NY, US
Jing Guo - Niskayuna NY, US
Luciana Meli - Albany NY, US
Nelson Felix - Slingerlands NY, US
International Classification:
H01L 21/033
H01L 21/027
Abstract:
A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Vertical Field-Effect-Transistors Having A Silicon Oxide Layer With Controlled Thickness

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US Patent:
20190189775, Jun 20, 2019
Filed:
Feb 22, 2019
Appl. No.:
16/282384
Inventors:
- Armonk NY, US
Sanjay MEHTA - Niskayuna NY, US
Luciana MELI - ALBANY NY, US
Muthumanickam SANKARAPANDIAN - Niskayuna NY, US
Kristin SCHMIDT - Mountain View CA, US
Ankit VORA - San Jose CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/66
H01L 29/08
H01L 29/78
H01L 21/8238
H01L 27/088
Abstract:
A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

Care Area Generation By Detection Optimized Methodology

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US Patent:
20190065634, Feb 28, 2019
Filed:
Aug 23, 2017
Appl. No.:
15/684006
Inventors:
- Armonk NY, US
Nelson Felix - Briarcliff Manor NY, US
Scott Halle - Slingerlands NY, US
Luciana Meli - Albany NY, US
International Classification:
G06F 17/50
Abstract:
A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.
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Luciana U Meli from Albany, NY, age ~47 Get Report