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Luc R Semeria

from Palo Alto, CA
Age ~50
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Also known as:
Luc R Semeia, Luc Semeira
Phone and address:
3370 Cork Oak Way, Palo Alto, CA 94303
(650) 922-0961
Related to:
George T Kupper, 88Jessica C MullenDarcy Kuhlengel, 71Evelyn KuhlengelKeith Kuhlengel, 68Dan Holton
Connected to:
Brian J Semeriglia, 47Elizabeth Semerjian, 62Greg Semerjian, 41Jonathan Semerjian, 28Scott E Semerod, 39Mackens Semerzier, 44Alyse N Semetosky, 37Jeanette Semexant, 66Veronica C Semey, 43Janice K Semeyn, 50

Luc Semeria Phones & Addresses

  • 3370 Cork Oak Way, Palo Alto, CA 94303 (650) 922-0961
  • Stanford, CA
  • 2402 Laura Ln, Mountain View, CA 94043 (650) 965-9213 (650) 966-1213
  • 925 Oak Ave, Menlo Park, CA 94025 (650) 325-2211
  • Los Altos, CA
  • Santa Clara, CA
  • 3370 Cork Oak Way, Palo Alto, CA 94303 (650) 965-9213

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Luc Semeria Photo 1

Engineering Manager - Gpu Software

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Location:
3370 Cork Oak Way, Palo Alto, CA 94303
Industry:
Computer Software
Work:
Agility Design Solutions Mar 2004 - Mar 2008
Staff
Synopsys Feb 2002 - Mar 2004
R and D Engineer
Clearwater Networks Xsteam Logic Feb 2001 - Jan 2002
Cad R and D Engineer
Stanford University Sep 1996 - Feb 2001
Researcher
Apple Sep 1996 - Feb 2001
Engineering Manager - Gpu Software
Education:
Stanford University Sep 1998 - Feb 2001
Doctorates, Doctor of Philosophy, Electrical Engineering Stanford University Sep 1996 - Jun 1998
Master of Science, Masters, Electrical Engineering Télécom Paris Sep 1993 - Jun 1996
Skills:
Software Development
Embedded Software
C++
Device Drivers
Matlab
Hardware Architecture
Computer Architecture
Signal Processing
Processors
Engineering
Perl
R&D
Cad
Languages:
English
Luc Semeria Photo 2

Luc Semeria

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Publications

Us Patents

Cache Drop Feature To Increase Memory Bandwidth And Save Power

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US Patent:
20180349291, Dec 6, 2018
Filed:
May 31, 2017
Appl. No.:
15/610008
Inventors:
- Cupertino CA, US
Kenneth C. Dyke - Los Altos CA, US
Karthik Ramani - San Jose CA, US
Winnie W. Yeung - San Jose CA, US
Anthony P. DeLaurier - Los Altos CA, US
Luc R. Semeria - Palo Alto CA, US
David A. Gotwalt - Winter Springs FL, US
Srinivasa Rangan Sridharan - San Jose CA, US
Muditha Kanchana - San Jose CA, US
International Classification:
G06F 12/123
G06F 12/0808
G06F 12/0815
G06F 12/0804
Abstract:
Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

Targeted Cache Flushing

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US Patent:
20180181491, Jun 28, 2018
Filed:
Dec 22, 2016
Appl. No.:
15/389153
Inventors:
- Cupertino CA, US
Luc R. Semeria - Palo Alto CA, US
Gokhan Avkarogullari - Cupertino CA, US
David A. Gotwalt - Winter Springs FL, US
Robert S. Hartog - Windermere FL, US
Michael J. Swift - San Francisco CA, US
International Classification:
G06F 12/0891
G06F 12/0895
Abstract:
Techniques are disclosed relating to flushing cache lines. In some embodiments, a graphics processing unit includes a cache and one or more storage elements configured to store a plurality of command buffers that include instructions executable to manipulate data stored in the cache. In some embodiments, ones of the cache lines in the cache are configured to store data to be operated on by instructions in the command buffers and a first tag portion that identifies a command buffer that has stored data in the cache line. In some embodiments, the graphics processing unit is configured to receive a request to flush cache lines that store data of a particular command buffer, and to flush ones of the cache lines having first tag portions indicating the particular command buffer as having data stored in the cache lines while maintaining data stored in other ones of the cache lines as valid.
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Luc R Semeria from Palo Alto, CA, age ~50 Get Report