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Louis J Nervegna

from Andover, MA
Age ~48
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Related to:
Frances M NervegnaMargaret NervegnaMary H Nervegna, 83
Connected to:
Ruben O Nervegna, 55Raeann K Nerveza, 35Christopher A Nervi, 51Constanza H Nervi, 52Sebastian Nervi, 47David W Nerviani, 72Janet M Nervick, 78Debbie R Nervig, 64Louise E Nervig, 78Callie M Nervik, 36

Louis Nervegna Phones & Addresses

  • Andover, MA
  • 505 Birch St, Scranton, PA 18505
  • Somerville, MA
  • 502 Gilmartin St #Rear Rear, Archbald, PA 18403 (570) 346-6175
  • Lackawaxen, PA

Education

Degree: Masters Degree School / High School: Massachusetts Institute of Technology 1999 to 2001 Specialities: Electrical Engineering & Computer Science

Skills

Mixed Signal

Industries

Semiconductors

Resumes

Resumes

Louis Nervegna Photo 1

Staff Design Engineer At Silicon Laboratories

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Location:
Greater Boston Area
Industry:
Semiconductors
Education:
Massachusetts Institute of Technology 1999 - 2001
Masters Degree, Electrical Engineering & Computer Science Massachusetts Institute of Technology 1995 - 2001
Bachelors Degree, Electrical Engineering
Skills:
Mixed Signal

Business Records

Name / Title
Company / Classification
Phones & Addresses
Louis Nervegna
Soc signatory
Boston Microtechnology
Semiconductors · Computer Related Services
15 New England Executive Park, Burlington, MA 01803
15 New England Exec Park, Burlington, MA 01803

Publications

Us Patents

Precision Oscillator Having Improved Temperature Coefficient Control

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US Patent:
7385453, Jun 10, 2008
Filed:
Mar 31, 2006
Appl. No.:
11/395378
Inventors:
Louis J. Nervegna - Somerville MA, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03L 1/00
US Classification:
331176, 331111, 331143, 331177 V
Abstract:
A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

Programmable Resistor Array Having Current Leakage Control

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US Patent:
7461285, Dec 2, 2008
Filed:
Mar 31, 2006
Appl. No.:
11/395366
Inventors:
Louis J. Nervegna - Somerville MA, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
G06F 1/00
H03L 1/00
US Classification:
713500, 331176
Abstract:
A free running clock circuit includes a programmable resistor array including a plurality of resistors connected in series. A plurality of transistors are connected to the plurality of resistors wherein each of the plurality of resistors has one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor and providing a resistance thereto. A transistor funnel limits leakage currents from a portion of the plurality of transistors to a single transistor of the transistor funnel.

Equalization In Clock Recovery Receivers

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US Patent:
7499489, Mar 3, 2009
Filed:
Sep 16, 2004
Appl. No.:
10/944279
Inventors:
William F. Ellersick - Sudbury MA, US
Louis Nervegna - Somerville MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 5/159
US Classification:
375229
Abstract:
Equalization techniques in clock recovery receivers may include use of a passive equalizer prior to amplification, combined frequency paths in and active and/or passive equalizer, capacitive degeneration and/or negative feedback with low-pass filtering in an active equalizer, a decision feedback equalizer with multiple decision paths, and programmable tail currents to change switching points. A compensation circuit for a pre/post equalizer may include an oscillator fabricated from replica components to compensate for process variations and a look-up table to provide process variation correction in response to programmed equalizer settings.

Programmable Precision Oscillator

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US Patent:
7649425, Jan 19, 2010
Filed:
Mar 31, 2006
Appl. No.:
11/395367
Inventors:
Louis J. Nervegna - Somerville MA, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03L 1/04
G06F 1/00
US Classification:
331176, 331111, 331143, 713500
Abstract:
A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage. The switching circuit has an inherent temperature profile associated therewith. A voltage divider circuit outputs a defined trip voltage that is compensated over the temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for the free running clock circuit. The voltage divider circuit has a top programmable resistor array connected in series with at least two programmable resistor arrays between two supply terminals of differing voltages.

Memory Power Controller

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US Patent:
8020010, Sep 13, 2011
Filed:
Jun 24, 2008
Appl. No.:
12/144803
Inventors:
Douglas F. Pastorello - Hudson NH, US
Patrick De Bakker - Hollis NH, US
Louis J. Nervegna - Andover MA, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
G06F 9/30
G06F 9/38
US Classification:
713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340, 327142, 327143
Abstract:
A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.

Charge Pump With Low Power, High Voltage Protection Circuitry

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US Patent:
8054125, Nov 8, 2011
Filed:
Dec 31, 2009
Appl. No.:
12/650756
Inventors:
Louis Nervegna - Andover MA, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
G05F 1/10
US Classification:
327536, 363 60
Abstract:
A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level. A second control circuit provides an indication that the charging voltage has reached a charging level for programming the OTP memory responsive to the determined charging voltage.

Hebbian Synapse Circuit

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US Patent:
20040139040, Jul 15, 2004
Filed:
Jan 5, 2004
Appl. No.:
10/751396
Inventors:
Louis Nervegna - Cambridge MA, US
Chi-Sang Poon - Lexington MA, US
International Classification:
G06F015/18
G06G007/00
G06N003/02
G06E003/00
G06E001/00
G06G007/58
G06G007/48
US Classification:
706/015000, 703/011000
Abstract:
A Hebbian synapse emulation circuit models the conductance of a synapse circuit. In one embodiment, the circuit includes a counter that provides control signals determining the conduction states of electrical pathways, which define the conductance level of the synapse. The counter can increment, decrement, or leave the same, the synapse conductance value based upon potentiation and depression signals that are derived from a voltage that corresponds to the calcium concentration in the synapse. The counter can be coupled to a plurality of synapse circuits on a time-shared basis.

Hebbian Synapse Circuit

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US Patent:
6687686, Feb 3, 2004
Filed:
Jul 6, 2000
Appl. No.:
09/611137
Inventors:
Louis Nervegna - Cambridge MA
Chi-Sang Poon - Lexington MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
G06N 302
US Classification:
706 15, 706 33, 706 40
Abstract:
A Hebbian synapse emulation circuit models the conductance of a synapse circuit. In one embodiment, the circuit includes a counter that provides control signals determining the conduction states of electrical pathways, which define the conductance level of the synapse. The counter can increment, decrement, or leave the same, the synapse conductance value based upon potentiation and depression signals that are derived from a voltage that corresponds to the calcium concentration in the synapse. The counter can be coupled to a plurality of synapse circuits on a time-shared basis.
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Louis J Nervegna from Andover, MA, age ~48 Get Report