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Lorimer K Hill

from Gardnerville, NV
Age ~92
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Also known as:
Kenneth Hill Lorimer, Hill Lorimer
Phone and address:
1040 Ranch Dr, Gardnerville, NV 89460
(775) 265-0000
Related to:
Rebekah D Hill, 48Roger K Hill, 64Lydia Hill
Connected to:
Abigail E Hill, 34Acacia L Hill, 59Addey P Hill, 33Addis J Hill, 78Aiden J Hill, 34Alease C Hill, 58Alena Hill, 49Alesecia T Hill, 39Alexandre M Hill, 37Alexandrea R Hill, 29

Lorimer Hill Phones & Addresses

  • 1040 Ranch Dr, Gardnerville, NV 89460 (775) 265-0000
  • 16004 Northstone Dr, Huntersville, NC 28078
  • 17442 Glassfield Dr, Huntersville, NC 28078
  • 10590 Castine Ave, Cupertino, CA 95014 (408) 732-1454
  • 2201 Laurelwood Rd, Santa Clara, CA 95054
  • 1040 Ranch Dr, Gardnerville, NV 89460

Work

Company: Siliconix 1969 to 1997 Position: Manager, ic design engineering

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: The University of Texas at Austin

Industries

Semiconductors

Resumes

Resumes

Lorimer Hill Photo 1

Lorimer Hill

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Location:
1040 Ranch Dr, Gardnerville, NV 89460
Industry:
Semiconductors
Work:
Siliconix 1969 - 1997
Manager, Ic Design Engineering
Education:
The University of Texas at Austin
Masters, Master of Science In Electrical Engineering

Publications

Us Patents

Integrated Buried Zener Diode And Temperature Compensation Transistor

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US Patent:
47664690, Aug 23, 1988
Filed:
Jan 6, 1986
Appl. No.:
6/816593
Inventors:
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H01L 2990
H01L 2972
H01L 2974
H01L 2702
US Classification:
357 13
Abstract:
A Zener diode (D) exhibiting subsurface breakdown includes a cathode (36) formed entirely within the emitter (22, 28) of a vertical PNP transistor (Q). The base (16) and collector (11) of the PNP transistor are resistively coupled to ground. The emitter of the PNP transistor functions as the anode of the Zener diode. Because of this, it is unecessary to provide an emitter contact. The PNP transistor compensates for changes in Zener breakdown voltage caused by changes in temperature. Because the PNP transistor is formed directly underneath the Zener diode, the temperature of the PNP transistor accurately tracks that of the Zener diode and therefore provides better temperature compensation. Also, because the cathode of the Zener diode is formed directly in the emitter of the PNP transistor, there is no lateral current flow and attendant voltage drop in the emitter of the PNP transistor.

Ion Implantation Of Thin Film Crsi.sub.2 And Sic Resistors

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US Patent:
47598360, Jul 26, 1988
Filed:
Aug 12, 1987
Appl. No.:
7/084541
Inventors:
Lorimer K. Hill - Cupertino CA
Barry L. Chin - Sunnyvale CA
Richard A. Blanchard - Los Altos CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
B05D 512
B05D 306
H01C 1706
US Classification:
20419221
Abstract:
A thin film resistor is formed using sputtering to deposit a thin film of resistive material on an insulating surface. The sputter target is composed of constituents which are normally present in relatively large quantities in thin film resistors, such as chromium silicide and silicon carbide. The sputtered thin film material is formed into resistor regions. An insulating layer is deposited over the thin film material. Ions (e. g. , boron ions) are then implanted into the thin film through the insulating layer. These implanted constituents have a significant effect on the temperature coefficient and sheet resistance of the thin film resistor. Ion implantation of these constituents enables more control over the characteristics of the thin film resistor as compared to prior art techniques not using ion implantation.

Power Supply Having Dual Ramp Control Circuit

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US Patent:
46740201, Jun 16, 1987
Filed:
Dec 13, 1985
Appl. No.:
6/808575
Inventors:
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H02M 3335
US Classification:
363 21
Abstract:
A power supply (100) includes a first lead (12) for receiving an input voltage (Vin) and an inductor (L1) and a switching transistor (Q1) coupled in series between the input lead and ground. The node (N1) between the inductor (L1) and switching transistor (Q1) is coupled through a diode (D1) to an output terminal (14). When the switching transistor is on current flow causes energy to be stored in the inductor. When the switching transistor turns off, the energy stored in the inductor is provided to a load (RL) coupled to the output terminal. The on-time of the transistor is controlled by a comparator (20) which receives a first voltage (V3) proportional to the current through the switching transistor and a second voltage (V4). The second voltage decreases linearly with respect to time at a rate dependent on the difference between the voltage at the output terminal (Vout) and a reference voltage (Vref). Because of this, the power supply is insensitive to voltage spikes which may appear on the first input lead of the comparator.

Hall Sensing Of Bond Wire Current

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US Patent:
50178040, May 21, 1991
Filed:
Apr 19, 1989
Appl. No.:
7/340445
Inventors:
James A. Harnden - Los Gatos CA
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H03K 1790
H03K 326
US Classification:
307309
Abstract:
A unique current sense means is provided in which a bonding wire or similar conductor is routed to one or more Hall effect current sensing devices which, in one embodiment, is fabricated as part of a power semiconductor device.

Method And Apparatus For Sampling And Holding An Analog Input Voltage Which Eliminates Offset Voltage Error

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US Patent:
41199600, Oct 10, 1978
Filed:
Feb 11, 1977
Appl. No.:
5/767735
Inventors:
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H03K 1309
US Classification:
340347AD
Abstract:
A sample and hold circuit uses two amplifiers the second being a Miller integrator and the first a comparator which compares the feed back stored capacitor voltage to the sampled voltage to bring the stored voltage of the capacitor to the sample voltage value. This stored voltage will have included in it the offset voltage of the first amplifier. However on readout this offset voltage is eliminated by disconnecting the sample input and also the connection between the output of the first amplifier and the input of the second and instead connecting the output of the first amplifier to the sample input and taking the output from this interconnection line. Since the noninverting or plus terminal of the first amplifier has impressed upon it the stored voltage of the capacitor the unwanted offset voltage is effectively subtracted. The foregoing sample and hold circuit also finds preferred use in a 12 bit recirculating A to D converter where cumulative offset errors would cause error. In such a configuration one of the sample and hold circuits can have the feedback interconnection of the first amplifier configured to perform suitable multiplication and subtraction, for example, for a Gray code.

Floating Drive Technique For Reverse Battery Protection

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US Patent:
55396100, Jul 23, 1996
Filed:
May 26, 1993
Appl. No.:
8/067365
Inventors:
Richard K. Williams - Cupertino CA
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix incorporated - Santa Clara CA
International Classification:
H02H 318
US Classification:
361246
Abstract:
A MOSFET is used to protect a battery driven load against the effects of a reverse-connected battery. This invention is particularly suitable for use with loads, such as those commonly found in motor vehicles, which contain semiconductor devices that may be severely damaged by a reverse voltage. The source of the MOSFET is connected to the positive terminal of the battery, and a gate driver circuit is used to provide a gate to source voltage sufficient to turn the MOSFET on when the battery is properly connected. If the battery is connected in reverse, the gate driver turns the MOSFET off, and the intrinsic body-drain diode in the MOSFET prevents a reverse current flow through the load. In conjunction with the MOSFET, a sensing device sends out a warning signal which may be used, for example, to turn off a portion of the load if the output of the battery falls below a level necessary to maintain the MOSFET in a fully on condition.

Switch Interface Circuit For Power Mosfet Gate Drive Control

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US Patent:
48535630, Aug 1, 1989
Filed:
Apr 10, 1987
Appl. No.:
7/036777
Inventors:
Lorimer K. Hill - Cupertino CA
James A. Harnden - San Jose CA
Barry J. Concklin - Sunnyvale CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H03K 1704
H03K 17687
US Classification:
307475
Abstract:
A switch interface circuit provides control voltages to the gate of a power MOSFET while protecting the power MOSFET from breakdown caused by transient signals and over-voltage. In one embodiment, a large JFET acts as gate-source shunt and a small JFET serves as a current source to turn the power MOSFET off when the turn-on current is removed. The JFET gate-drain and gate-source breakdown provides a voltage limitation to protect the MOSFET from gate overvoltage. Alternatively, Zener diodes and MOS transistors are used in lieu of the JFET for shorting the power MOSFET gate to source during turn-off and limiting its gate to source voltage during turn-on.

Quantized Feedback Analog To Digital Converter With Offset Voltage Compensation

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US Patent:
41647335, Aug 14, 1979
Filed:
Apr 29, 1977
Appl. No.:
5/792351
Inventors:
George F. Landsburg - Cupertino CA
Lorimer K. Hill - Cupertino CA
Assignee:
Siliconix Inc. - Santa Clara CA
International Classification:
H03K 1302
US Classification:
340347NT
Abstract:
Analog to digital converter of the type in which an analog input signal is integrated and charge is applied to the integrating capacitor in predetermined measured quantities to offset or balance the effect of the input signal. A counter is incremented and decremented in accordance with the balancing charge to provide a count corresponding to the input signal. Means is included for eliminating errors due to offset voltages and imperfections in the virtual ground of the integrator, and the operating level of the integrator during a conversion is set independently of the sources which supply the balancing charge.
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Lorimer K Hill from Gardnerville, NV, age ~92 Get Report