US Patent:
20080320016, Dec 25, 2008
Inventors:
Gaurav Singh - Los Altos CA, US
Srivatsan Srinivasan - San Jose CA, US
Lintsung Wong - Santa Clara CA, US
Assignee:
Raza Microelectronics, Inc. - Cupertino CA
International Classification:
G06F 17/30
G06F 12/00
G06F 9/30
US Classification:
707100, 711104, 712220, 711160, 707E17044, 711E12001, 712E09016
Abstract:
An apparatus for queue scheduling. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The queue controller interfaces with the queue and the dispatch order data structure. Multiple queue structures interfaces with an output arbitration logic and schedule packets to achieve optimal throughput.