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Lintsung L Wong

from San Jose, CA
Age ~48

Lintsung Wong Phones & Addresses

  • 2823 Lavender Ter, San Jose, CA 95111 (408) 247-7973
  • Santa Clara, CA
  • Fremont, CA
  • Union City, CA
  • Goleta, CA
  • Sunnyvale, CA
  • Newport Beach, CA
  • 2823 Lavender Ter, San Jose, CA 95111

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Publications

Us Patents

Age Matrix For Queue Entries Dispatch Order

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US Patent:
8285974, Oct 9, 2012
Filed:
Jul 30, 2007
Appl. No.:
11/830727
Inventors:
Gaurav Singh - Los Altos CA, US
Srivatsan Srinivasan - San Jose CA, US
Lintsung Wong - Santa Clara CA, US
Assignee:
NetLogic Microsystems, Inc. - Irvine CA
International Classification:
G06F 9/30
US Classification:
712214
Abstract:
An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.

Age Matrix For Queue Dispatch Order

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US Patent:
20080320016, Dec 25, 2008
Filed:
Aug 29, 2007
Appl. No.:
11/847170
Inventors:
Gaurav Singh - Los Altos CA, US
Srivatsan Srinivasan - San Jose CA, US
Lintsung Wong - Santa Clara CA, US
Assignee:
Raza Microelectronics, Inc. - Cupertino CA
International Classification:
G06F 17/30
G06F 12/00
G06F 9/30
US Classification:
707100, 711104, 712220, 711160, 707E17044, 711E12001, 712E09016
Abstract:
An apparatus for queue scheduling. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The queue controller interfaces with the queue and the dispatch order data structure. Multiple queue structures interfaces with an output arbitration logic and schedule packets to achieve optimal throughput.

Age Matrix For Queue Dispatch Order

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US Patent:
20080320274, Dec 25, 2008
Filed:
Jun 19, 2007
Appl. No.:
11/820350
Inventors:
Gaurav Singh - Los Altos CA, US
Srivatsan Srinivasan - San Jose CA, US
Lintsung Wong - Santa Clara CA, US
Assignee:
Raza Microelectronics, Inc. - Cupertino CA
International Classification:
G06F 9/30
US Classification:
712 23, 712E09086
Abstract:
An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
Lintsung L Wong from San Jose, CA, age ~48 Get Report