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Linda E Zalzala

from Cedar Park, TX
Age ~59
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Also known as:
Linda Ellen Zalzala
Phone and address:
12011 Taku Rd, Cedar Park, TX 78613
Related to:
Ali A Zalzala, 62
Connected to:
Jim Zalzalah, 61Neam Zalzala, 47Sidrah N Zalzala, 73Michal Zalzman, 51Cin Zam, 51Jennifer J Zam, 54Sean L Zam, 46Cromwell N Zama, 56Mohammad A Zama, 45Christine M Zamagias, 61

Linda Zalzala Phones & Addresses

  • 12011 Taku Rd, Cedar Park, TX 78613
  • 3005 Taku Rd, Cedar Park, TX 78613
  • Austin, TX
  • Round Rock, TX

Work

Company: Ericsson Position: Asic design manager

Education

Degree: Graduate or professional degree

Emails

l***[email protected]

Resumes

Resumes

Linda Zalzala Photo 1

Asic Design Manager

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Location:
Cedar Park, TX
Work:
Ericsson
Asic Design Manager

Business Records

Name / Title
Company / Classification
Phones & Addresses
Linda Zalzala
Governing, Governing Person
ALZ COMMERCIAL GROUP, LLC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
PO Box 441, Cedar Park, TX 78630
3005 Taku Rd, Cedar Park, TX 78613

Publications

Us Patents

Method Of Data Communication Flow Control In A Data Processing System Using Busy/Ready Commands

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US Patent:
6157967, Dec 5, 2000
Filed:
Dec 30, 1997
Appl. No.:
9/001100
Inventors:
Robert W. Horst - Saratoga CA
William Edward Baker - Austin TX
Linda Ellen Zalzala - Austin TX
William Patterson Bunton - Austin TX
Richard W. Cutts - Georgetown TX
David J. Garcia - Los Gatos CA
John C. Krause - Georgetown TX
Stephen G. Low - Austin TX
David Paul Sonnier - Austin TX
William Joel Watson - Austin TX
Patracia L. Whiteside - Austin TX
Assignee:
Tandem Computer Incorporated - Cupertino CA
International Classification:
G06F 1100
H04L 116
US Classification:
710 19
Abstract:
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Network Message Routing Using Routing Table Information And Supplemental Enable Information For Deadlock Prevention

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US Patent:
59149531, Jun 22, 1999
Filed:
Jun 7, 1995
Appl. No.:
8/474772
Inventors:
John C. Krause - Georgetown TX
David J. Garcia - Los Gatos CA
Robert W. Horst - Saratoga CA
Geoffrey I. Iswandhi - Sunnyvale CA
David Paul Sonnier - Austin TX
William Joel Watson - Austin TX
Linda Ellen Zalzala - Austin TX
Assignee:
Tandem Computers, Inc. - Santa Clara CA
International Classification:
H04L 1200
US Classification:
370392
Abstract:
A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.

Synchronized Data Transmission Between Elements Of A Processing System

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US Patent:
55748490, Nov 12, 1996
Filed:
Jun 7, 1995
Appl. No.:
8/482628
Inventors:
David P. Sonnier - Austin TX
Wiliam P. Bunton - Austin TX
Richard W. Cutts - Georgetown TX
James S. Klecka - Lexington TX
John C. Krause - Georgetown TX
William J. Watson - Austin TX
Linda E. Zalzala - Austin TX
Assignee:
Tandem Computers Incorporated - Cupertino CA
International Classification:
G01R 3128
G06F 1100
US Classification:
3951821
Abstract:
Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.

Detecting And Isolating Errors Occurring In Data Communication In A Multiple Processor System

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US Patent:
61516899, Nov 21, 2000
Filed:
Dec 9, 1996
Appl. No.:
8/762653
Inventors:
David J. Garcia - Los Gatos CA
William Patterson Bunton - Austin TX
John Deane Coddington - Cedar Park TX
John C. Krause - Georgetown TX
Susan Stone Meredith - Hillsboro OR
David P. Sonnier - Austin TX
William Joel Watson - Austin TX
Linda Ellen Zalzala - Austin TX
Assignee:
Tandem Computers Incorporated - Cupertino CA
International Classification:
H02H 305
US Classification:
714 49
Abstract:
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Apparatus For Detecting Divergence Between A Pair Of Duplexed, Synchronized Processor Elements

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US Patent:
57907765, Aug 4, 1998
Filed:
Jun 7, 1995
Appl. No.:
8/485053
Inventors:
David Paul Sonnier - Austin TX
William Edward Baker - Austin TX
William Patterson Bunton - Austin TX
John C. Krause - Georgetown TX
Kenneth H. Porter - Austin TX
William Joel Watson - Austin TX
Linda Ellen Zalzala - Austin TX
Assignee:
Tandem Computers Incorporated - Cupertino CA
International Classification:
G06F 1100
US Classification:
39518908
Abstract:
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-Fast, Fail-Functional, Fault-Tolerant Multiprocessor System

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US Patent:
57519323, May 12, 1998
Filed:
Jun 7, 1995
Appl. No.:
8/485217
Inventors:
Robert W. Horst - Saratoga CA
William Edward Baker - Austin TX
Randall G. Banton - Hopkinton MA
John Michael Brown - Austin TX
William F. Bruckert - Austin TX
William Patterson Bunton - Austin TX
Gary F. Campbell - Palo Alto CA
John Deane Coddington - Cedar Park TX
Richard W. Cutts - Georgetown TX
Barry Lee Drexler - Austin TX
Harry Frank Elrod - Austin TX
Daniel L. Fowler - Georgetown TX
David J. Garcia - Los Gatos CA
Paul N. Hintikka - Austin TX
Geoffrey I. Iswandhi - Sunnyvale CA
Douglas Eugene Jewett - Round Rock TX
Curtis Willard Jones - Austin TX
James Stevens Klecka - Lexington TX
John C. Krause - Georgetown TX
Stephen G. Low - Austin TX
Susan Stone Meredith - Hillsboro OR
Steven C. Meyers - Round Rock TX
David P. Sonnier - Austin TX
William Joel Watson - Austin TX
Patricia L. Whiteside - Austin TX
Frank A. Williams - Austin TX
Linda Ellen Zalzala - Austin TX
Assignee:
Tandem Computers Incorporated - Cupertino CA
International Classification:
G06F 1100
US Classification:
3951821
Abstract:
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
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Linda E Zalzala from Cedar Park, TX, age ~59 Get Report