Search

Liang Kuo Chen

from Union City, CA
Age ~56
Get Report
Also known as:
Liang K Chen, Chen Kuo Liang, Kuoliang G Chen, Chen Chen Liang, Liang Chen Kuo, Kuo Liang Chen, Kuoliang L Chen, Liang Chen Kuoliang, Lian Chen
Related to:
Lily L Chan, 54Tina WenKuo Liang ChenAriel Chen, 50Hsiufen Yang, 72Hui Wen Chang, 58Hui Chang WenWen Chang JuiChia C Chen, 53
Connected to:
Abre G Chen, 65Adele Chen, 52Adeline K Chen, 39Ai M Chen, 60Ai C Chen, 79Aiping Chen, 63Alen Y Chen, 68Alma Chen, 29Amanda Chen, 44Amanda T Chen, 63

Liang Chen Phones & Addresses

  • Union City, CA
  • Burlingame, CA
  • San Mateo, CA
  • Millbrae, CA
  • El Cerrito, CA
  • 604 Portsmouth Ln, Foster City, CA 94404

Professional Records

License Records

Liang Chen

License #:
010919 - Active
Category:
WELDER
Issued Date:
Oct 7, 2016
Expiration Date:
Oct 7, 2019

Medicine Doctors

Liang Chen Photo 1

Liang Chen

View page
Specialties:
Family Medicine
Work:
Baptist Primary Care GroupBaptist Primary Care
440 Kingsley Ave, Orange Park, FL 32073
(904) 264-9293 (phone), (904) 264-7553 (fax)
Languages:
English
French
Description:
Ms. Chen works in Orange Park, FL and specializes in Family Medicine. Ms. Chen is affiliated with Orange Park Medical Center.

Resumes

Resumes

Liang Chen Photo 2

Liang Chen Sunnyvale, CA

View page
Work:
Rambus

2011 to 2000
Senior Manager - IP Strategy
BMO Capital Markets

2010 to 2000
Equity Research Associate - Semiconductors
TCL Corporation

2009 to 2010
Director of Digital Home Strategy
California Public Employees' Retirement System (CalPERS)
Sacramento, CA
Jun 2008 to Aug 2008
Equity Research Intern
Intel
Santa Clara, CA
2003 to 2008
Staff Design Engineer / Lab Manager
Conexant Systems / Rockwell Semiconductor System
San Diego, CA
1998 to 2002
Senior Design Engineer
Hewlett-Packard Singapore (Pte) Ltd.
Singapore
1995 to 1996
Test Engineer
Education:
University of California
Berkeley, CA
2006 to 2008
MBA
University of Massachusetts at Amherst
Amherst, MA
1996 to 1998
M.S. in Electrical and Computer Engineering
Tsinghua University
Bachelor of Engineering in Electrical Engineering
Skills:
Equity research, financial modeling, valuation, strategic planning, market research, competitive analysis, Excel, Word, PowerPoint

Business Records

Name / Title
Company / Classification
Phones & Addresses
Liang Chen
President
Creative Gift
PO Box 55555, Hayward, CA 94545
Liang Light Chen
President
SIX SIGHTS CORPORATION
Whol Electronic Parts/Equipment
16799 Potter Ct, Los Gatos, CA 95032
(408) 402-0611
Liang Chen
President
AMERICAN HEALTH PRODUCTS, INC
533 Airport Blvd STE 400, Burlingame, CA 94010
Liang Chen
President
MC ENTERPRISE GROUP, INC
Business Services · Whol Plumbing Equipment/Supplies
4323 Moorpark Ave STE B, San Jose, CA 95129
Liang Chen
President
AMERICAN HEALTH PRODUCTS OF CALIFORNIA, INC
63 Bovet Rd #514, San Mateo, CA 94402
520 S El Camino Real, San Mateo, CA 94402
Liang T. Chen
President
BLESYS INC
13795 Calle Tacuba Dr, Saratoga, CA 95070
13795 Calle Tacuba, Saratoga, CA 95070
Liang Gong Chen
President
JIANGUO TECHNOLOGY INC
855 Ln Playa #462, San Francisco, CA 94121

Publications

Us Patents

Method For Enhancing The Adhesion Of Copper Deposited By Chemical Vapor Deposition

View page
US Patent:
6362099, Mar 26, 2002
Filed:
Mar 9, 1999
Appl. No.:
09/265290
Inventors:
Srinivas Gandikota - Santa Clara CA
Dennis Cong - Sunnyvale CA
Liang Chen - Foster City CA
Sesh Ramaswami - Saratoga CA
Daniel Carl - Pleasanton CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 2322
US Classification:
438687, 438653
Abstract:
The present invention provides a method for improving the adhesion of copper and other metal-comprising conductive metals to a barrier layer. A barrier layer is provided that has a first surface that is substantially unoxidized, wherein at least a portion of the first surface is free from the presence of oxygen atoms. A conductive layer is then deposited onto the first surface of the barrier layer. The substantially unoxidized state of the first surface enhances the adhesion of the metal-comprising layer to the barrier layer. The method is particularly useful in obtaining excellent adhesion of a copper nucleation layer to an underlying barrier layer surface.

Method For Achieving Copper Fill Of High Aspect Ratio Interconnect Features

View page
US Patent:
6436267, Aug 20, 2002
Filed:
Aug 29, 2000
Appl. No.:
09/650108
Inventors:
Daniel A. Carl - Pleasanton CA
Barry Chin - Saratoga CA
Liang Chen - San Jose CA
Robin Cheung - Cupertino CA
Peijun Ding - San Jose CA
Yezdi Dordi - Palo Alto CA
Imran Hashim - San Jose CA
Peter Hey - Sunnyvale CA
Ashok K. Sinha - Palo Alto CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 2802
US Classification:
205186, 205123, 205157
Abstract:
One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

Method And Apparatus For Cycle-Based Computation

View page
US Patent:
7036114, Apr 25, 2006
Filed:
Mar 29, 2002
Appl. No.:
10/113005
Inventors:
Thomas M. McWilliams - Menlo Park CA, US
Jeffrey B. Rubin - Pleasanton CA, US
Derek E. Pappas - Union City CA, US
Oyekunle A. Olukotun - Stanford CA, US
Jeffrey M. Broughton - Palo Alto CA, US
David R. Emberson - Santa Cruz CA, US
William kwei-cheung Lam - Newark CA, US
Liang T. Chen - Saratoga CA, US
Ihao Chen - San Jose CA, US
Earl T. Cohen - Fremont CA, US
Michael W. Parkin - Palo Alto CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717149, 717136, 719152
Abstract:
A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Method And Apparatus For Simulation Processor

View page
US Patent:
7043596, May 9, 2006
Filed:
Mar 29, 2002
Appl. No.:
10/113060
Inventors:
Thomas M. McWilliams - Menlo Park CA, US
Jeffrey B. Rubin - Pleasanton CA, US
Michael W. Parkin - Palo Alto CA, US
Oyekunle A. Olukotun - Stanford CA, US
Derek E. Pappas - Union City CA, US
Jeffrey M. Broughton - Palo Alto CA, US
David R. Emberson - Santa Cruz CA, US
David S. Allison - San Ramon CA, US
Ashley N. Saulsbury - Los Gatos CA, US
Earl T. Cohen - Fremont CA, US
Nyles I. Nettleton - Campbell CA, US
James B. Burr - Foster City CA, US
Liang T. Chen - Saratoga CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 13/00
H04L 12/28
US Classification:
710317, 370351
Abstract:
A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Method And Apparatus For Evaluating Logic States Of Design Nodes For Cycle-Based Simulation

View page
US Patent:
7076416, Jul 11, 2006
Filed:
Mar 25, 2002
Appl. No.:
10/105754
Inventors:
Liang T. Chen - Saratoga CA, US
William kwei-cheung Lam - Newark CA, US
Thomas M. McWilliams - Menlo Park CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
703 15, 703 13, 703 14, 703 16, 703 2, 716 3, 716 4, 716 7, 717141
Abstract:
A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.

Method And Apparatus For Simulation System Compiler

View page
US Patent:
7080365, Jul 18, 2006
Filed:
Mar 29, 2002
Appl. No.:
10/113582
Inventors:
Jeffrey M. Broughton - Palo Alto CA, US
Liang T. Chen - Saratoga CA, US
William kwei-cheung Lam - Newark CA, US
Derek E. Pappas - Union City CA, US
Ihao Chen - San Jose CA, US
Thomas M. McWilliams - Menlo Park CA, US
Ankur Narang - New Delhi, IN
Jeffrey B. Rubin - Pleasanton CA, US
Earl T. Cohen - Fremont CA, US
Michael W. Parkin - Palo Alto CA, US
Ashley N. Saulsbury - Los Gatos CA, US
Michael S. Ball - La Mesa CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717146, 716 1, 703 15
Abstract:
A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Method And Apparatus For Accelerated Post-Silicon Testing And Random Number Generation

View page
US Patent:
7133818, Nov 7, 2006
Filed:
Apr 17, 2003
Appl. No.:
10/417765
Inventors:
Keith H. Bierman - San Jose CA, US
David R. Emberson - Santa Cruz CA, US
Liang T. Chen - Saratoga CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
703 17, 703 14, 703 15, 702117, 702119, 702120, 716 4
Abstract:
A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Method For Providing Cycle-By-Cycle Ad Hoc Verification In A Hardware-Accelerated Environment

View page
US Patent:
7155378, Dec 26, 2006
Filed:
Dec 16, 2002
Appl. No.:
10/320108
Inventors:
Liang T. Chen - Saratoga CA, US
David R. Emberson - Santa Cruz CA, US
Keith H. Bierman - San Jose CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 17/50
G06F 9/45
US Classification:
703 14, 716 4, 716 5
Abstract:
A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.

Isbn (Books And Publications)

Chinese Grain Economy and Policy

View page
Author

Liang Yu Chen

ISBN #

0851986420

Amazon

Oriental Style

Oriental Style

View page

To the world at large, Oriental style has increasingly becomes less remote, mysterious and inaccessible; instead, it represents a culturally significant approach to decoration that can easily be adapted to modern lifestyles.  It is a decorative style that not only projects a traditional Chinese aest...
Author

Chen Ci Liang, Zhang Shu Hong, Dawn Teo

Binding

Hardcover

Pages

240

Publisher

Page One Publishing

ISBN #

9812453741

EAN Code

9789812453747

ISBN #

10

Contemporary Teahouses In China

Contemporary Teahouses In China

View page

The history of tea culture runs long and deep in China it is not only a traditional art form intertwined with daily living, but drinking tea also serves as a way for the contemporary Chinese to relax. As China is the original land of tea culture, its teahouses are primarily concerned with spreading...
Binding

Hardcover

Pages

240

Publisher

Page One Publishing

ISBN #

9812451218

EAN Code

9789812451217

ISBN #

8

Practical Handbook Of Advanced Interventional Cardiology: Tips And Tricks

Practical Handbook of Advanced Interventional Cardiology: Tips and Tricks

View page

Written and edited by today's most-recognized inteventional cardiology thought leaders, this popular guide focuses on key procedures and techniques. Each strategic or tactical move is graded by complexity level and described in a simple, step-by-step approach that includes guidance on how to overcom...
Author

Thach Nguyen, Dayi Hu, Shao Liang Chen, Moo-Hyun Kim, Shigeru Saito, Cindy Grines, C. Michael Gibson, Steven R. Bailey

Binding

Paperback

Pages

712

Publisher

Wiley-Blackwell

ISBN #

0470670479

EAN Code

9780470670477

ISBN #

1

Control profile
Liang Kuo Chen from Union City, CA, age ~56 Get Report