Resumes
Resumes
Li-Yuan Chen Phones & Addresses
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7720 Orogrande Pl, Cupertino, CA 95014
Publications
Us Patents
Fifo Memory Devices And Methods Of Operating Fifo Memory Devices Having Multi-Port Cache Memory Devices Therein
View pageUS Patent:
6754777, Jun 22, 2004
Filed:
Dec 2, 2002
Appl. No.:
10/307638
Inventors:
Mario Au - Fremont CA
Li-Yuan Chen - Cupertino CA
Li-Yuan Chen - Cupertino CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G06F 1208
US Classification:
711131, 711120, 710 52
Abstract:
A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port. The multiplexer is responsive to at least one path select signal and has a first input electrically coupled to the data output of the data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of the retransmit register.
Fifo Memory Devices Having Multi-Port Cache And Extended Capacity Memory Devices Therein With Retransmit Capability
View pageUS Patent:
6874064, Mar 29, 2005
Filed:
Apr 5, 2004
Appl. No.:
10/818018
Inventors:
Mario Au - Fremont CA, US
Li-Yuan Chen - Cupertino CA, US
Li-Yuan Chen - Cupertino CA, US
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G06F012/08
G11C007/10
G11C007/10
US Classification:
711131, 711120, 710 52
Abstract:
A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e. g. , SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level. The multiplexer is also configured to block the first memory path and enable a direct path that routes second data from the data input register to the data output port during second FIFO read operations that occur when the FIFO memory device is almost empty.
Multi-Port Cache Memory Devices And Fifo Memory Devices Having Multi-Port Cache Memory Devices Therein
View pageUS Patent:
6546461, Apr 8, 2003
Filed:
Nov 22, 2000
Appl. No.:
09/721478
Inventors:
Mario Au - Fremont CA
Li-Yuan Chen - Cupertino CA
Li-Yuan Chen - Cupertino CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G06F 1208
US Classification:
711131, 711120, 710 52, 36518902
Abstract:
A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port. The multiplexer is responsive to at least one path select signal and has a first input electrically coupled to the data output of the data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of the retransmit register.