Inventors:
Leonid B. Sassoon - Gold River CA
Assignee:
Level One Communications, Inc. - Sacremento CA
International Classification:
G04F 800
G04F 1000
G03L 700
H04L 700
Abstract:
A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an input signal timing variation. A verification is performed to insure the second output signal conforms to timing of a predetermined output signal. The input signal produces the first output signal by acquiring the input signal in a first buffer in response to a first signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first signal. The first output signal is transferred from the second buffer to a third buffer in response to a second signal to produce a second output signal. The second output signal is resistant to a plurality of clock and data skews. A comparison of a predetermined input signal to the second output signal to determine if the second output signal will appear at the output at the predetermined time.