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Leonard W Schaper

from Naples, FL
Age ~79
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Also known as:
Leonard R Schaper, Leonard Schaper Revocable, Leonard Schaper Ret, Louise R Schaper, Leo R Schaper
Phone and address:
516 Neapolitan Ln, Naples, FL 34103
(479) 236-5943
Related to:
Alfred B Southall, 87David Whitesell, 59Claire Moitra, 48Michael Schaper, 48Irene SchaperMicheal Schaper, 49
Connected to:
Andy Schaper, 49Catherine E Schaper, 55Diana C Schaper, 84Dina C Schaper, 63Glenn A Schaper, 67Jacob Schaper, 94Joyce I Schaper, 97Juergen H Schaper, 102Martin Schaper, 68Michah A Schaperjahn, 41

Leonard Schaper Phones & Addresses

  • 516 Neapolitan Ln, Naples, FL 34103 (479) 236-5943
  • Lee, MA
  • Providence, RI
  • Fayetteville, AR
  • Poway, CA
  • Millburn, NJ
  • Berkeley Heights, NJ
  • West Orange, NJ

Work

Company: Schaper consulting Dec 2008 Position: Professor emeritus; consultant, electronic packaging

Education

Degree: Dr. Engr. Sc. School / High School: New Jersey Institute of Technology 1970 to 1973 Specialities: Engineering

Skills

University Teaching • Engineering Management • Experimentation • Electronics Packaging • Research Management • Data Analysis • Sensors • Mems • Electronics • Materials • Engineering • Thin Films • Characterization • Expert Witness • Design of Experiments • Microelectronics • Simulations • Semiconductors • Product Development • Research • Patents • Analysis • Electronic Packaging Analysis

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Leonard Schaper Photo 1

Professor Emeritus; Consultant, Electronic Packaging

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Location:
Naples, FL
Industry:
Electrical/Electronic Manufacturing
Work:
Schaper Consulting since Dec 2008
Professor Emeritus; Consultant, Electronic Packaging
University of Arkansas Dec 1992 - Dec 2008
Professor
Alcoa Electronic Packaging 1990 - 1992
Director, Thin Film
AT&T Bell Laboratories 1986 - 1990
Head, Technical Program Analysis Department
Education:
New Jersey Institute of Technology 1970 - 1973
Dr. Engr. Sc., Engineering Massachusetts Institute of Technology 1967 - 1968
SMEE, Electrical Engineering New Jersey Institute of Technology 1963 - 1967
BSEE, Electrical Engineering
Skills:
University Teaching
Engineering Management
Experimentation
Electronics Packaging
Research Management
Data Analysis
Sensors
Mems
Electronics
Materials
Engineering
Thin Films
Characterization
Expert Witness
Design of Experiments
Microelectronics
Simulations
Semiconductors
Product Development
Research
Patents
Analysis
Electronic Packaging Analysis

Business Records

Name / Title
Company / Classification
Phones & Addresses
Leonard W. Schaper
OZARK CHORAL SOCIETY, INC
34 E Ctr St, Fayetteville, AR 72701
Leonard W Schaper
XANODICS, LLC
700 Research Ctr Blvd, Fayetteville, AR 72701
Leonard W Schaper
Secretary, President
SCHAPER CONSULTING, INC
516 Neopolitan Ln, Naples, FL 34103
2650 Gulfshore Blvd N, Naples, FL 34103

Publications

Us Patents

Electronic Interconnection Medium Having Offset Electrical Mesh Plane

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US Patent:
6388200, May 14, 2002
Filed:
Apr 25, 2001
Appl. No.:
09/841601
Inventors:
Leonard W. Schaper - Fayetteville AR
Assignee:
The Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H05K 163
US Classification:
174255, 174261, 174262, 361805, 361794, 361795
Abstract:
An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors. Another embodiment provides arranging touching conductive regions, defining signal path areas along uniformly-spaced touching borders, and then carving away conductive material to form desirably positioned and spaced power, ground and signal conductors.

Method Of Making Capacitor With Extremely Wide Band Low Impedance

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US Patent:
6516504, Feb 11, 2003
Filed:
Oct 19, 1999
Appl. No.:
09/421120
Inventors:
Leonard W. Schaper - Fayetteville AR
Assignee:
The Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H05G 700
US Classification:
29 2542, 361304, 3613062, 427 79, 427 81
Abstract:
A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than -40 dB over a range from 1 GHz to 10 GHz.

Surface Applied Passives

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US Patent:
6707680, Mar 16, 2004
Filed:
Mar 5, 2002
Appl. No.:
10/090933
Inventors:
Leonard W. Schaper - Fayetteville AR
Assignee:
Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H05K 710
US Classification:
361760, 361763, 361734, 361766, 361720, 257762, 257765, 257677, 174 521
Abstract:
Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Apparatus And Method For Providing Low-Loss Transmission Lines In Interconnected Mesh Plane Systems

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US Patent:
6800939, Oct 5, 2004
Filed:
May 29, 2002
Appl. No.:
10/156772
Inventors:
Leonard W. Schaper - Fayetteville AR
Assignee:
The Board of Trustees for the University of Arkansas - Fayetteville AR
International Classification:
H01L 23485
US Classification:
257758, 257659, 257664, 361777, 361778, 174261
Abstract:
An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Decoupling Capacitor For Integrated Circuit Package And Electrical Components Using The Decoupling Capacitor And Associated Methods

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US Patent:
6806568, Oct 19, 2004
Filed:
Jul 20, 2001
Appl. No.:
09/908751
Inventors:
Leonard W. Schaper - Fayetteville AR
Assignee:
The Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H01L 2334
US Classification:
257724, 257528, 257532, 257535
Abstract:
A capacitive structure is made with thin film capacitor plates substantially surrounding an opening cavity for accommodating a chip. The capacitive structure includes at least one capacitor and is mounted around the periphery of a ball grid array (BGA) having a flip chip in the opening. The capacitive structure provides a high capacitance with a low parasitic inductance.

Rc Terminator And Production Method Therefor

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US Patent:
7005722, Feb 28, 2006
Filed:
Jan 26, 2001
Appl. No.:
10/182142
Inventors:
Leonard W. Schaper - Fayetteville AR, US
James Patrick Parkerson - Fayetteville AR, US
Assignee:
The Board of Trustees of the University of Arkansas - Fayetteville AR
International Classification:
H01L 29/00
US Classification:
257533, 257536, 257537, 257307
Abstract:
A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein.

Method Of Packaging Rf Mems

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US Patent:
7049175, May 23, 2006
Filed:
Nov 6, 2002
Appl. No.:
10/494956
Inventors:
Leonard W. Schaper - Fayetteville AR, US
Ajay P. Malshe - Fayetteville AR, US
Chad O'Neal - Farmington AR, US
Assignee:
Board of Trustees of the University of Arkansas - Fayetteville AR
International Classification:
H01L 21/48
US Classification:
438113, 438458, 438459, 438460
Abstract:
A structure and process for packaging RF MEMS and other devices employs a substrate of silicon, for example, and a cap of glass, for example, having cavities to receive the devices. MEMS or other devices are supported on an upper surface of the substrate, into which metal-filled blind vias are formed. The cap is attached to the substrate, so as to enclose designated MEMS or other devices in the cavities. The substrate is then thinned so as to expose the metal of the vias at a lower surface of the substrate. Electrical connecting elements such as solder balls are then applied to the metal of the vias. The resultant composite substrate is then divided to provide individual packaged devices.

Electronic Interconnection Medium Having Offset Electrical Mesh Plane

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US Patent:
20010047588, Dec 6, 2001
Filed:
Jun 22, 2001
Appl. No.:
09/885981
Inventors:
Leonard Schaper - Fayetteville AR, US
Assignee:
The Board of Trustees of the University of Arkansas
International Classification:
H05K003/02
H05K003/20
US Classification:
029/847000, 029/846000, 029/852000, 029/831000
Abstract:
An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors. Another embodiment provides arranging touching conductive regions, defining signal path areas along uniformly-spaced touching borders, and then carving away conductive material to form desirably positioned and spaced power, ground and signal conductors.

Isbn (Books And Publications)

Integrated Passive Component Technology

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Author

Leonard W. Schaper

ISBN #

0471244317

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Leonard W Schaper from Naples, FL, age ~79 Get Report