Leon Parisoe

from Raleigh, NC

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Leon Parisoe Phones & Addresses

15509 Possum Track Rd, Raleigh, NC 27614
1516 Beacon Ridge Rd, Charlotte, NC 28210

Work

Company: Coventor Jan 1998 Position: Software design engineer at coventor

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: Florida Institute of Technology

Skills

Software Development • Software Engineering • C++ • Agile Methodologies • Linux • Perl • Testing • Wireless • Java • C • Embedded Systems • Gnu Debugger • Algorithms • Software Design • Eda • Python

Industries

Computer Software

Resumes

Software Design Engineer At Coventor

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Location:

625 Mount Auburn St, Cambridge, MA 02138

Industry:

Computer Software

Work:

Coventor
Software Design Engineer at Coventor

Education:

Florida Institute of Technology
Bachelors, Bachelor of Science In Electrical Engineering

Skills:

Software Development
Software Engineering
C++
Agile Methodologies
Linux
Perl
Testing
Wireless
Java
C
Embedded Systems
Gnu Debugger
Algorithms
Software Design
Eda
Python

Business Records

Name / Title

Company / Classification

Phones & Addresses

Leon F. Parisoe
Principal

Appointment Congo
Business Services at Non-Commercial Site

12417 Moriah Way, Raleigh, NC 27614

Publications

Us Patents

Arithmetic Logic Unit

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US Patent:

45596085, Dec 17, 1985

Filed:

Jan 21, 1983

Appl. No.:

6/460061

Inventors:

William R. Young - Palm Bay FL
Leon F. Parisoe - Raleigh NC

Assignee:

Harris Corporation - Melbourne FL

International Classification:

G05F 750

US Classification:

364786

Abstract:

An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transition of the precharged RAM outputs to the desired outputs are used to trigger the logic. Latches, which are an integral part of the output of the propagate and generate signal section and are latched by the high/low transition of the output and reset by precharge signal, are used in combination with a special control sequence of the logic select of the propagate and generate section to isolate the latch and output such that one of the buses though the ALU may be used as a bidirectional bus so that the ALU may write back into the RAM without intermediate registers or latches. To reduce the length of interconnects and number of crossovers when the ALU includes a shifter/swapper for BCD operations, the carry and sum logic units are grouped by nibbles and are interleaved. Also, the carry and sum logic of nibbles other than the first nibble have carry look ahead logic such that only a single delay is experienced per nibble to produce a carry nibble.