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Lena M Ahlen

from La Grange, TX
Age ~54
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Also known as:
Lena Maria Ahlen, Lena Maria Vance, Lena M Vance, Lena Ahlen Gross, Lena A Gross, Lena S, Maria Lena Vance, Maria Vance
Related to:
Genella T Doucet, 81Sande K VanceLena M Vance, 54Thomas E Vance, 62Jerrod W Gross, 56Gina M Vance, 59Lisa G Rushing, 62Donnye Vance, 61
Connected to:
Lars G Ahlen, 36Shawne K Ahlenius, 63Delmar H Ahleong, 44Jennifer M Ahler, 43Justin Ahler, 33Rachel A Ahler, 34Kent R Ahlering, 44Ashley J Ahlers, 34Barbara J Ahlers, 82Brennen W Ahlers, 38

Lena Ahlen Phones & Addresses

  • La Grange, TX
  • Austin, TX
  • Houston, TX
  • Beaumont, TX
  • Palmdale, CA

Interests

job inquiries, reference requests, getti...

Industries

Semiconductors

Resumes

Resumes

Lena Ahlen Photo 1

Member Of Technical Staff At Amd Member Of Technical Staff At Advanced Micro Devices

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Location:
Austin, Texas Area
Industry:
Semiconductors
Experience:
AMD (Public Company; AMD; Semiconductors industry): Member of Technical Staff,  (1997-Present) Advanced Micro Devices (Public Company; Semiconductors industry): Member of Technical Staff,  (1997-Present) 

Publications

Us Patents

Voltage Source For Gate Oxide Protection

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US Patent:
20090184696, Jul 23, 2009
Filed:
Jan 23, 2008
Appl. No.:
12/018297
Inventors:
Dimitry Patent - Austin TX, US
Ravinder Rachala - Austin TX, US
Shawn Searles - Austin TX, US
Lena Ahlen - La Grange TX, US
Matthew Cooke - Austin TX, US
International Classification:
G05F 1/10
US Classification:
323265
Abstract:
An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node

Method And Apparatus For Adjusting A Timing Derate For Static Timing Analysis

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US Patent:
20170185709, Jun 29, 2017
Filed:
Mar 13, 2017
Appl. No.:
15/456634
Inventors:
- Cambridge, GB
Karen Lee DELK - Austin TX, US
Lena AHLEN - Austin TX, US
James Dennis DODRILL - Austin TX, US
International Classification:
G06F 17/50
Abstract:
A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Method For Adjusting A Timing Derate For Static Timing Analysis

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US Patent:
20160357894, Dec 8, 2016
Filed:
Aug 18, 2016
Appl. No.:
15/239991
Inventors:
- Cambridge, GB
Karen Lee DELK - Austin TX, US
Lena AHLEN - Austin TX, US
James Dennis DODRILL - Austin TX, US
International Classification:
G06F 17/50
Abstract:
A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Method For Adjusting A Timing Derate For Static Timing Analysis

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US Patent:
20150370955, Dec 24, 2015
Filed:
Jun 18, 2014
Appl. No.:
14/307646
Inventors:
- Cambridge, GB
Lena AHLEN - Austin TX, US
International Classification:
G06F 17/50
Abstract:
A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.
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Lena M Ahlen from La Grange, TX, age ~54 Get Report