Lee S Tavrow

58058389, Sep 8, 1998

May 31, 1996

8/655999

Ivan E. Sutherland - Santa Monica CA
Lee S. Tavrow - Sunnyvale CA

Sun Microsystems, Inc. - Palo Alto CA

H01J 1300

395292

Improved circuits for implementing various embodiments of high performance arbiters are disclosed. In one embodiment, a late-done arbiter is implemented by combining a late-decision arbiter with a decision storage (or queue) device. In another embodiment, an arbiter implementation that extends the amount of storage available for decisions is disclosed. A decision making device such as a simple arbiter is followed by a decision storage device such as a queue or a first in first out (FIFO) register of any number of stages. The decision storage device following the arbiter allows the arbiter to report each decision as quickly as it can and to start the next decision making cycle.

57425566, Apr 21, 1998

Dec 26, 1996

8/773393

Lee Stuart Tavrow - Sunnyvale CA
Mark Ronald Santoro - Sunnyvale CA

Micro Magic, Inc. - Sunnyvale CA

G11C 800

3652257

An integrated circuit memory structure includes a plurality of regular columns of memory cells arranged as a sequence such that each regular column except the last in the sequence has an associated adjacent regular column. Each regular column has associated sense amplifier circuitry and write driver circuitry for, respectively, reading output data from and writing input data to the regular column. At least one redundant column of memory cells is also provided. The structure also includes a programmable element that responds to a programming stimulus by providing a programming signal that identifies one of the regular columns as a defective column. Reconfiguration circuitry responds to the programming signal by reconfiguring the memory structure such that the sense amplifier circuitry and the write driver circuitry of each regular column in the sequence, beginning with the defective column, is reconfigured to be associated with the adjacent regular column. The sense amplifier circuitry associated with the last regular column in the sequence is reconfigured to be associated with the redundant column, which has its own associated write driver. The concepts of column redundancy are also applicable to row redundancy.

51131170, May 12, 1992

Sep 8, 1989

7/404741

Rodney A. Brooks - Lincoln MA
Lee S. Tavrow - Somerville MA
Anita M. Flynn - Arlington MA

Massachusetts Institute of Technology - Cambridge MA

H01L 4108

310328

An electrical device comprises a three-dimensional body formed from an organic polymer and a plurality of electrical elements attached to the body. The body has a regular pattern of sockets in its surface, and the electrical elements have barbed appendages, or, alternatively, the body has appendages and the electrical elements have sockets. The elements are affixed to the body by insertion of the appendages into the sockets. Electrical connections between the electrical elements are formed by selective deposition of tungsten onto the surface of the body with a scanning laser beam. A miniature ("gnat") robot can be constructed using those constructional techniques.

54851068, Jan 16, 1996

Apr 5, 1994

8/222988

Robert J. Drost - Santa Clara CA
David M. Murata - San Jose CA
Robert J. Bosnyak - Sunnyvale CA
Mark R. Santoro - Sunnyvale CA
Lee S. Tavrow - Sunnyvale CA

Sun Microsystems, Inc. - Mountain View CA

H03K 190175
H03K 19082
H03K 190948

326 66

An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and V. sub. DD.

54023866, Mar 28, 1995

Jul 15, 1993

8/091948

Lee S. Tavrow - Sunnyvale CA
Mark R. Santoro - Sunnyvale CA
Gary W. Bewick - Palo Alto CA

Sun Microsystems, Inc. - Mountain View CA

G11C 1140

36523006

A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

52930947, Mar 8, 1994

Dec 5, 1990

7/626224

Anita M. Flynn - Arlington MA
Lee S. Tavrow - Somerville MA
Rodney A. Brooks - Lincoln MA
Leslie E. Cross - State College PA
Stephen F. Bart - Watertown MA

Massachusetts Institute of Technology - Cambridge MA

H01L 4108

310323

A ferroelectric motor comprises a single layer of ferroelectric material electrically excited by an array of electrical contacts and an electrical excitation source for supplying phased electrical signals to the contacts thereby creating a travelling wave of mechanical deformation in the ferroelectric layer and actuating an actuator. In alternative embodiments of the invention, the actuator may be linear or rotary. The motor may be fabricated on a single integrated circuit die, in which case the layer of ferroelectric material may be a thin film of PZT. In other embodiments a motor may comprise two dies which are sandwiched together by wafer to wafer bonding. Portions of a die may be removed to permit a linear actuator to project beyond the die.

53813774, Jan 10, 1995

Sep 27, 1993

8/131058

Gary W. Bewick - Palo Alto CA
Mark R. Santoro - Sunnyvale CA
Lee S. Tavrow - Sunnyvale CA

Sun Microsystems, Inc. - Mountain View CA

G11C 1140

36523006

A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.

62223836, Apr 24, 2001

Dec 26, 1996

8/773136

David Minoru Murata - San Jose CA
Mark Ronald Santoro - Sunnyvale CA
Lee Stuart Tavrow - Sunnyvale CA

Micro Magic, INc. - Sunnyvale CA

H03K 19094
H03K 19177

326 44

A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane. The NOR gate further includes a PMOS load transistor having its source connected to a voltage supply, its drain connected to the NOR gate output node and its gate connected to receive a timing signal that turns on the PMOS load transistor as the minterms are generated at the output of the AND plane and turns off the PMOS load transistor when the sum of products are provided at the output latches.