Search

Larry R Fenstermaker

from Nazareth, PA
Age ~73
Get Report
Also known as:
Larry B Fenstermaker, Lawrence R Fenstermaker, Laurence R Fenstermaker
Phone and address:
356 Meyer Rd, Nazareth, PA 18064
(610) 759-2111
Related to:
Zachery R Rich, 29Allison Blackwood, 48Bradley Anderson, 46Sheldon Anderson, 76Allison AndersonAbe Anderson, 76
Connected to:
Alan Fenster, 84Alouise L Fenstermacher, 94Alyson Fenstermacher, 40Amy J Fenstermacher, 54Blanche B Fenster, 59Brenda A Fenstermaker, 57Briana L Fenstermacher, 37Cara L Fenstermacher, 47Charles R Fensterman, 75Chelsea E Fenstermaker, 38

Larry Fenstermaker Phones & Addresses

  • 356 Meyer Rd, Nazareth, PA 18064 (610) 759-2111
  • Edgewood, MD
  • Whitehall, PA
  • Northampton, PA

Work

Company: Lattice semiconductor Position: Other

Education

Degree: Graduate or professional degree

Skills

Circuit Design • Cmos • Simulation • Static Timing Analysis • Electrical Engineering • Electronics • Unix • C • Semiconductors • Simulations • Asic • Fpga • Verilog • Mixed Signal • Embedded Systems • Soc • Eda • Vlsi • Rtl Design • Timing Closure • Analog • Integrated Circuit Design • Physical Design

Industries

Semiconductors

Resumes

Resumes

Larry Fenstermaker Photo 1

Larry Fenstermaker

View page
Location:
356 Meyer Rd, Nazareth, PA 18064
Industry:
Semiconductors
Work:
Lattice Semiconductor
Other
Skills:
Circuit Design
Cmos
Simulation
Static Timing Analysis
Electrical Engineering
Electronics
Unix
C
Semiconductors
Simulations
Asic
Fpga
Verilog
Mixed Signal
Embedded Systems
Soc
Eda
Vlsi
Rtl Design
Timing Closure
Analog
Integrated Circuit Design
Physical Design

Business Records

Name / Title
Company / Classification
Phones & Addresses
LARRY FENSTERMAKER
CONTROLLER
SOLT
819 Nazareth Pike, Nazareth, PA 18064
(610) 759-1000
Larry Fenstermaker
Controller, CONTROLLER
Solt Chevrolet Oldsmobile, Inc
Ret New/Used Automobiles Misc Bus Credit Instn
PO Box 265, Nazareth, PA 18064
819 Nazareth Pike, Nazareth, PA 18064
(610) 759-1000

Publications

Us Patents

Programmable Logic Devices With Integrated Standard-Cell Logic Blocks

View page
US Patent:
6870395, Mar 22, 2005
Filed:
Mar 18, 2003
Appl. No.:
10/391094
Inventors:
John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H01L025/00
H03K019/177
H03K017/693
G06F017/50
US Classification:
326 41, 716 14, 716 16
Abstract:
A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Bi-Directional Buffering For Memory Data Lines

View page
US Patent:
6882555, Apr 19, 2005
Filed:
Jun 18, 2003
Appl. No.:
10/464083
Inventors:
Larry R. Fenstermaker - Nazareth PA, US
Zheng Chen - Macungie PA, US
Gregory S. Cartney - Coplay PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G11C005/06
US Classification:
365 63, 3652335
Abstract:
Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.

Programmable Logic Devices With Integrated Standard-Cell Logic Blocks

View page
US Patent:
6975137, Dec 13, 2005
Filed:
Feb 10, 2005
Appl. No.:
11/055280
Inventors:
John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F007/38
G06F017/50
H03K019/177
H03K019/00
US Classification:
326 39, 716 16
Abstract:
A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Programmable Logic Device Having A Configurable Dram With Transparent Refresh

View page
US Patent:
7129749, Oct 31, 2006
Filed:
Oct 27, 2004
Appl. No.:
10/974305
Inventors:
Larry R. Fenstermaker - Nazareth PA, US
John A. Schadt - Bethlehem PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 82
Abstract:
A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.

Low Power Asynchronous Sense Amp

View page
US Patent:
7161862, Jan 9, 2007
Filed:
Nov 22, 2004
Appl. No.:
10/996283
Inventors:
Mou C. Lin - High Bridge NJ, US
Zheng Chen - Macungie PA, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G11C 7/02
US Classification:
365207, 365205
Abstract:
A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.

Address Isolation For User-Defined Configuration Memory In Programmable Devices

View page
US Patent:
7196963, Mar 27, 2007
Filed:
Oct 17, 2005
Appl. No.:
11/251682
Inventors:
Larry R. Fenstermaker - Nazareth PA, US
Sajitha Wijesuriya - Macungie PA, US
Harold N. Scholz - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G11C 8/00
G11C 7/10
US Classification:
36523005, 36518904, 36518908
Abstract:
In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.

Interface Circuitry For Electrical Systems

View page
US Patent:
7215149, May 8, 2007
Filed:
Dec 15, 2004
Appl. No.:
11/012550
Inventors:
William B. Andrews - Emmaus PA, US
Larry R. Fenstermaker - Nazareth PA, US
John Schadt - Bethlehem PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/0175
US Classification:
326 83, 326 81
Abstract:
An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

Dynamic Over-Voltage Protection Scheme For Integrated-Circuit Devices

View page
US Patent:
7230810, Jun 12, 2007
Filed:
Dec 9, 2004
Appl. No.:
11/007954
Inventors:
William B. Andrews - Emmaus PA, US
Mou C. Lin - High Ridge NJ, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H02H 9/04
US Classification:
361 911
Abstract:
An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.
Control profile
Larry R Fenstermaker from Nazareth, PA, age ~73 Get Report