Lark E Lehman

6560137, May 6, 2003

Jan 16, 2001

09/764223

Judith E. Allen - Monument CO
Lark E. Lehman - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

G11C 1122

365145, 365205, 36518521, 3651852, 365207

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

7453285, Nov 18, 2008

Dec 22, 2006

11/615382

Steven Lee Kiel - Littleton CO,
Douglas Norman Krening - Larkspur CO,
Lark Edward Lehman - Colorado Springs CO,
Michael Joseph Schneiderwind - Castle Rock CO,

Chaologix, Inc. - Gainesville FL

H03K 19/173

326 38, 326 46

A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

20050122765, Jun 9, 2005

Nov 18, 2004

10/993202

Judith Allen - Monument CO,
Dennis Wilson - Woodland Park CO,
William Kraus - Palmer Lake CO,
Lark Lehman - Monument CO,

G11C011/22

365145000

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

60287837, Feb 22, 2000

Nov 14, 1997

8/970520

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

G11C 700

365145

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

59869194, Nov 16, 1999

Nov 14, 1997

8/970518

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

G11C 700

365145

A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

62527932, Jun 26, 2001

Sep 15, 2000

9/663121

Judith E. Allen - Monument CO
William F. Kraus - Colorado Springs CO
Lark E. Lehman - Colorado Springs CO
Dennis R. Wilson - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

G11C 700

365145

A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

RE351377, Jan 2, 1996

Dec 16, 1992

7/991682

Mark A. Bryans - Dallas TX
James H. Cline - Allen TX
Francis B. Frazee - Plano TX
Lark E. Lehman - Colorado Springs CO

Texas Instruments Incorporated - Dallas TX

H04L 2549

375293

A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.

58809899, Mar 9, 1999

Nov 14, 1997

8/970453

Dennis R. Wilson - Colorado Springs CO
William F. Kraus - Colorado Springs CO
Lark Edward Lehman - Colorado Springs CO

Ramtron International Corporation - Colorado Springs CO

G11C 700

365145

A method of operating a 1T/1C ferroelectric memory having a memory cell coupled to a word line, a bit line, and a plate line, includes the steps of turning on the word line, energizing the plate line to establish a charge on the bit line, turning off the word line, and sensing the charge on the bit line while the word line is off.