Lalitkumar Y Nathawad

7728631, Jun 1, 2010

May 15, 2008

12/120827

Lalitkumar Nathawad - Costa Mesa CA, US

Atheros Communications, Inc. - Santa Clara CA

H03D 13/00

327 12, 327 3, 327 7

A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

7728676, Jun 1, 2010

Apr 30, 2008

12/112914

Lalitkumar Nathawad - Costa Mesa CA, US
Justin Hwang - Mountain View CA, US

Atheros Communications, Inc. - Santa Clara CA

H03L 7/00

331 16, 331 17, 331167, 331117 R, 331177 R

A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

8010072, Aug 30, 2011

Jun 18, 2008

12/141499

Lalitkumar Nathawad - Costa Mesa CA, US

Atheros Communications, Inc. - San Jose CA

H04B 1/06
H04B 7/00

455260, 455254, 455255, 455258, 455259, 4551803, 4551821, 4551831, 331 18, 331 25, 331 34

A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.

8106479, Jan 31, 2012

Oct 1, 2008

12/243146

Lalitkumar Nathawad - Costa Mesa CA, US

Qualcomm Atheros, Inc. - San Jose CA

H01L 27/00

257533

Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

8107913, Jan 31, 2012

May 7, 2009

12/437442

Lalitkumar Nathawad - Fremont CA, US

Qualcomm Atheros, Inc. - San Jose CA

H04B 1/06

455255, 455256

A digital regulated Local Oscillator (LO) buffer receives an unregulated LO signal from a local oscillator to create a regulated LO signal. Embodiments include not only the digital regulated LO buffer, but also a transceiver and/or a receiver including at least one instance of the digital LO buffer. They may be implemented as an integrated circuit. The digital regulated LO Buffer may include: A LO buffer receiving the unregulated LO signal and an amplitude control signal to create the regulated LO signal. A peak detector receives the regulated LO signal to create an analog peak signal that is presented to a digital output comparator along with a reference amplitude signal to create a digital threshold detect signal. An amplitude controller receives the digital threshold detect signal to create a digital control signal that drives a digitally controlled source to create the amplitude control signal.

8187944, May 29, 2012

Dec 29, 2011

13/340622

Lalitkumar Nathawad - Costa Mesa CA, US

Qualcomm Atheros, Inc. - San Jose CA

H01L 27/00
H01L 21/20

438381

Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

20130007489, Jan 3, 2013

Jul 2, 2012

13/540488

Manoj Unnikrishnan - Santa Clara CA, US
Sarvesh Shrivastava - Sunnyvale CA, US
Lalitkumar Nathawad - Fremont CA, US

Qualcomm Atheros, Inc. - San Jose CA

G06F 1/32

713320

In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.

20130203369, Aug 8, 2013

Feb 7, 2012

13/368009

Hakan Dogan - El Cerrito CA, US
Lalitkumar Y. Nathawad - Fremont CA, US

QUALCOMM ATHEROS, INC. - San Jose CA

H04B 1/10

455132

A mechanism is disclosed for improving the performance of a coexisting radio by integrating a notch filter into an LNA of a first coexisting radio of two or more coexisting radios. The notch filter may be a differential circuit or a single-ended circuit. The single-ended circuit filters common mode signals. In one embodiment, the first coexisting radio has a carrier frequency that is in 2.4 GHz ISM frequency band and one of the other two or more coexisting radios has a carrier frequency that is in 1.9 GHz cellular band.