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Lakshmi Supriya

from Allston, MA
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Connected to:
Eko Supriyanto, 53Sherry L Suprock, 65Daniel F Suprun, 44Katherine Suprun, 71Serge Suprun, 48Ellen K Suprunowicz, 63Karen L Supry, 72Randolph Supry, 62Vincent A Suprynowicz, 101Johan Supuwood, 41

Lakshmi Supriya Phones & Addresses

  • Allston, MA
  • Chandler, AZ
  • 88 Beacon St, Arlington, MA 02474

Work

Company: T-mobile, ga May 2012 Position: Sr. sql server/ssis/ssrs developer

Education

School / High School: J.N. Technological University- Kakinada, Andhra Pradesh Specialities: Bachelor of Science in Electronics and Communications

Resumes

Resumes

Lakshmi Supriya Photo 1

Jawaharlal Nehru Technological

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Work:

Jawaharlal Nehru Technological
Lakshmi Supriya Photo 2

Lakshmi Supriya

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Work:
T-Mobile, GA

May 2012 to 2000
Sr. SQL Server/SSIS/SSRS Developer
Verint, GA

Jan 2011 to May 2012
SQL BI Developer, SSRS developer
Richo EWS, CA

Jun 2009 to Dec 2010
SQL BI Developer
SSRS

Oct 2006 to May 2009
Reporting Developer
Education:
J.N. Technological University
Kakinada, Andhra Pradesh
Bachelor of Science in Electronics and Communications

Publications

Us Patents

Microball Attachment Using Self-Assembly For Substrate Bumping

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US Patent:
7651021, Jan 26, 2010
Filed:
Dec 28, 2007
Appl. No.:
11/966943
Inventors:
Lakshmi Supriya - Chandler AZ, US
Ravi Nalla - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B23K 31/02
US Classification:
22818022, 228246, 2282481
Abstract:
Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.

Forming Vias Using Sacrificial Material

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US Patent:
7727886, Jun 1, 2010
Filed:
Jun 29, 2007
Appl. No.:
11/824212
Inventors:
Lakshmi Supriya - Chandler AZ, US
Omar J. Bchir - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/4763
US Classification:
438637, 438618, 257E21585, 257E21587
Abstract:
In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.

Apparatus And Methods Of Forming An Interconnect Between A Workpiece And Substrate

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US Patent:
7843075, Nov 30, 2010
Filed:
May 1, 2008
Appl. No.:
12/151063
Inventors:
Lakshmi Supriya - Chandler AZ, US
Anna M. Prakash - Chandler AZ, US
Tommy L. Ashton - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/40
H01L 21/44
US Classification:
257779, 257E23023, 257E21508, 438612
Abstract:
Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Multiple Die Structure And Method Of Forming A Connection Between First And Second Dies In Same

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US Patent:
8017498, Sep 13, 2011
Filed:
Sep 22, 2008
Appl. No.:
12/284531
Inventors:
Lakshmi Supriya - Arlington MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/30
US Classification:
438456, 438457, 438458, 438618, 257737, 257E5104, 257E51039
Abstract:
A multiple die structure includes a first die (), a second die (), a carbon nanotube () having a first end () in physical contact with the first die and having a second end () in physical contact with the second die, and an electrically conductive material () in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure () in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.

Method Of Forming An Interconnect Joint

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US Patent:
8124517, Feb 28, 2012
Filed:
Jul 16, 2010
Appl. No.:
12/837574
Inventors:
Lakshmi Supriya - Arlington MA, US
Daewoong Suh - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438597, 428328, 428323, 428209, 428560, 257E21495, 438623
Abstract:
A method of forming an interconnect joint includes providing a first metal layer (), providing a film () including metal particles () and organic molecules (), placing the film over the first metal layer, placing a second metal layer () over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Methods To Fabricate Functionally Gradient Materials And Structures Formed Thereby

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US Patent:
8173259, May 8, 2012
Filed:
Sep 27, 2007
Appl. No.:
11/863122
Inventors:
Lakshmi Supriya - Chandler AZ, US
Linda A. Shekhawat - Tucson AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B32B 5/66
US Classification:
428403, 428323, 428407
Abstract:
Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of functionalized nanaparticles on a substrate by immersing the substrate in at least one of a solvent and a polymer matrix, wherein at least one of the solvent and the polymer matrix comprises a plurality of functionalized nanoparticles; and forming a second layer of functionalized nanoparticles on the first layer of functionalized particles, wherein there is a gradient in a property between the first layer and the second layer.

Apparatus And Methods Of Forming An Interconnect Between A Workpiece And Substrate

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US Patent:
8183697, May 22, 2012
Filed:
Nov 30, 2010
Appl. No.:
12/956141
Inventors:
Lakshmi Supriya - Chandler AZ, US
Anna M. Prakash - Chandler AZ, US
Tommy Ashton, II - Mesa AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/40
H01L 21/44
US Classification:
257779, 438612, 257E23023, 257E21508
Abstract:
Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Methods Of Processing A Thermal Interface Material

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US Patent:
8383459, Feb 26, 2013
Filed:
Jun 24, 2008
Appl. No.:
12/145364
Inventors:
Lakshmi Supriya - Arlington MA, US
Jessica Weninger - Chicago IL, US
Leonel Arana - Phoenix AZ, US
Lateef Mustapha - Oro Valley AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438118, 438122
Abstract:
Methods are disclosed to process a thermal interface material to achieve easy pick and placement of the thermal interface material without lowering thermal performance of a completed semiconductor package. One method involves applying a non-adhesive layer on one or more surfaces of the thermal interface material, interfacing the thermal interface material with one or more components to interface the non-adhesive layer therebetween, and applying heat to alter the non-adhesive layer to increase thermal contact between the thermal interface material and the interfacing component(s).
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Lakshmi Supriya from Allston, MA Get Report