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Lakshmi Shiva Prasad Reddy

from Austin, TX
Age ~42
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Also known as:
Lakshmi Shiva Reddy, Lakshmi Prasad Reddy, Lakshmi S Reddy, Lakshmi Shiva Prasad, Lakshmi Shivaprasadreddy, Lakshmi S Prasad, Reddy Lakshmi Shiva, Shiva Laksh
Related to:
Brooke E Kattner, 30Venk ReddyBrandon T Kattner, 32Lance R Kattner, 55Vimal K Reddy, 47Diana L Kattner, 55Randall L Kattner, 81Neema Reddy, 52Neema Reddy
Connected to:
Aarathi A Reddy, 53Abhijith R Reddy, 35Adi K Reddy, 61Adla D Reddy, 126Adrienne F Reddy, 68Agara Reddy, 75Ahir K Reddy, 33Ajaykumar G Reddy, 41Alicia D Reddy, 38Alisa R Reddy, 58

Lakshmi Reddy Phones & Addresses

  • Austin, TX
  • Cary, NC
  • Cupertino, CA
  • 308 Entrada Way, Round Rock, TX 78681 (512) 953-1469
  • Raleigh, NC
  • Yakima, WA
  • Menlo Park, CA
  • Wade, NC

Professional Records

Medicine Doctors

Lakshmi Reddy Photo 1

Lakshmi K. Reddy

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Specialties:
Family Medicine
Work:
Primary Care Health Services IncEast End Community Health Center
117 N Negley Ave, Pittsburgh, PA 15206
(412) 404-4000 (phone), (412) 404-4004 (fax)
Education:
Medical School
University of Miami, Miller School of Medicine
Graduated: 2000
Procedures:
Allergen Immunotherapy
Destruction of Benign/Premalignant Skin Lesions
Electrocardiogram (EKG or ECG)
Hearing Evaluation
Psychological and Neuropsychological Tests
Vaccine Administration
Conditions:
Abnormal Vaginal Bleeding
Acute Bronchitis
Acute Pharyngitis
Acute Upper Respiratory Tract Infections
Atopic Dermatitis
Languages:
Arabic
English
Spanish
Description:
Dr. Reddy graduated from the University of Miami, Miller School of Medicine in 2000. She works in Pittsburgh, PA and specializes in Family Medicine. Dr. Reddy is affiliated with UPMC Shadyside.
Lakshmi Reddy Photo 2

Lakshmi P. Reddy

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Specialties:
Allergy & Immunology
Work:
Pediatric Endocrine Specialists Georgia
10700 Medlock Brg Rd STE 102, Duluth, GA 30097
(678) 691-5351 (phone), (770) 685-1241 (fax)

Allergy & Asthma Institute Johns Creek
10700 Medlock Brg Rd STE 102, Duluth, GA 30097
(678) 615-7878 (phone), (770) 685-1241 (fax)
Education:
Medical School
Meharry Medical College School of Medicine
Graduated: 2001
Procedures:
Allergen Immunotherapy
Allergy Testing
Pulmonary Function Tests
Vaccine Administration
Conditions:
Chronic Sinusitis
Contact Dermatitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Allergic Rhinitis
Languages:
English
Description:
Dr. Reddy graduated from the Meharry Medical College School of Medicine in 2001. She works in Duluth, GA and 1 other location and specializes in Allergy & Immunology.
Lakshmi Reddy Photo 3

Lakshmi K. Reddy

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Specialties:
Internal Medicine
Work:
Houston Internal Medicine Associates PA
21336 Provincial Blvd, Katy, TX 77450
(281) 809-0085 (phone), (281) 809-0083 (fax)
Education:
Medical School
Gandhi Med Coll, Ntr Univ of Hlth Sci, Hyderabad, Ap, India
Graduated: 1997
Conditions:
Acute Pancreatitis
Acute Pharyngitis
Acute Renal Failure
Anemia
Anxiety Dissociative and Somatoform Disorders
Languages:
English
Description:
Dr. Reddy graduated from the Gandhi Med Coll, Ntr Univ of Hlth Sci, Hyderabad, Ap, India in 1997. She works in Katy, TX and specializes in Internal Medicine. Dr. Reddy is affiliated with CHI St Lukes Health The Vintage Hospital, Houston Methodist West Hospital, Houston Methodist Willowbrook Hospital and North Cypress Medical Center.

Publications

Us Patents

Post-Placement Cell Shifting

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US Patent:
8495534, Jul 23, 2013
Filed:
Jun 8, 2010
Appl. No.:
12/796550
Inventors:
Charles J. Alpert - Austin TX, US
Zhuo D. Li - Austin TX, US
Gi-Joon Nam - Austin TX, US
Shyam Ramji - Hopewell Junction NY, US
Lakshmi N. Reddy - Yorktown Heights NY, US
Jarrod A. Roy - Austin TX, US
Taraneh E. Taghavi - San Diego CA, US
Paul G. Villarrubia - Austin TX, US
Natarajan Viswanathan - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716106, 716110, 716111, 716122, 716132
Abstract:
A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

Evaluating Routing Congestion Based On Average Global Edge Congestion Histograms

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US Patent:
8584070, Nov 12, 2013
Filed:
Oct 4, 2011
Appl. No.:
13/252868
Inventors:
Charles J. Alpert - Austin TX, US
Zhuo Li - Cedar Park TX, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Chin Ngai Sze - Austin TX, US
Yaoguang Wei - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716129, 716126, 716131
Abstract:
Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e. g. , 0. 5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

Identifier Binding For Automated Web Processing

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US Patent:
20100088752, Apr 8, 2010
Filed:
Oct 3, 2008
Appl. No.:
12/245688
Inventors:
Vikram Nagulakonda - Sunnyvale CA, US
Venkata Subba Rao Ravilisetty - Dublin CA, US
Lakshmi Narasimha Reddy Ankireddipally - Sunnyvale CA, US
International Classification:
H04L 9/32
G06F 21/20
US Classification:
726 6, 726 7
Abstract:
A process for the automatic handling of requests has a first step of receiving a session request, which results in the issuance of a session token. Upon receipt of a content transfer message accompanied by the previously issued session token, a routing tuple identifying a sender, receiver, and type, the content transfer message also containing content to be transferred, the routing tuple is compared to entries in a process table which resolves into an action and destination. The action and destination associated with the routing tuple and request type are performed if a match is found, or a default action is taken if no match is found, such as placing the content in a user INBOX for future handling. Additionally, the later actions the user takes on the INBOX are examined, and new entries are created in the process table based on the user actions.

Post-Placement Cell Shifting

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US Patent:
20130346938, Dec 26, 2013
Filed:
May 24, 2013
Appl. No.:
13/902303
Inventors:
Zhuo D Li - Austin TX, US
Gi-Joon Nam - Austin TX, US
Shyam Ramji - Hopewell Junction NY, US
Lakshmi N Reddy - Yorktown Heights NY, US
Jarrod A Roy - Austin TX, US
Taraneh E Taghavi - San Diego CA, US
Paul G Villarrubia - Austin TX, US
Natarajan Viswanathan - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716125
Abstract:
A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

Decision Intelligence System And Method

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US Patent:
20200210857, Jul 2, 2020
Filed:
Dec 31, 2019
Appl. No.:
16/731965
Inventors:
- Pleasanton CA, US
Ryan Andrew Oattes - Burlington, CA
Lakshmi Prasad Reddy Nanga - Pleasanton CA, US
Luis Antonio Monterrubio Ruiz - Burlington, CA
International Classification:
G06N 5/02
G06N 20/00
Abstract:
A decision intelligence system permits a data expert to input information to define business questions and a business knowledge model. A semantic ontology is generated from the business knowledge model. The business knowledge model is mapped to data sources and used to generate information for generating APIs for generating views of business data, such as machine generated data.

Integrated Circuit Buffering Solutions Considering Sink Delays

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US Patent:
20180373813, Dec 27, 2018
Filed:
Jun 22, 2017
Appl. No.:
15/630343
Inventors:
- Armonk NY, US
Stephen T. Quay - Austin TX, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Gustavo E. Tellez - Essex Junction VT, US
Gi-Joon Nam - Chappaqua NY, US
Jiang Hu - College Station TX, US
International Classification:
G06F 17/50
Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Integrated Circuit Buffering Solutions Considering Sink Delays

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US Patent:
20180373814, Dec 27, 2018
Filed:
Dec 20, 2017
Appl. No.:
15/848053
Inventors:
- Armonk NY, US
Stephen T. Quay - Austin TX, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Gustavo E. Tellez - Essex Junction VT, US
Gi-Joon Nam - Chappaqua NY, US
Jiang Hu - College Station TX, US
International Classification:
G06F 17/50
Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Integrated Circuit Buffering Solutions Considering Sink Delays

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US Patent:
20180373815, Dec 27, 2018
Filed:
Feb 14, 2018
Appl. No.:
15/896176
Inventors:
- Armonk NY, US
Stephen T. Quay - Austin TX, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Gustavo E. Tellez - Essex Junction VT, US
Gi-Joon Nam - Chappaqua NY, US
Jiang Hu - College Station TX, US
International Classification:
G06F 17/50
Abstract:
Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.
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Lakshmi Shiva Prasad Reddy from Austin, TX, age ~42 Get Report