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Kyle S Tsukamoto

from San Jose, CA
Age ~66

Kyle Tsukamoto Phones & Addresses

  • 1471 Rosecrest Ter, San Jose, CA 95126 (408) 294-0789
  • 171 Woodhams Rd, Santa Clara, CA 95051 (408) 246-5320
  • Stanford, CA

Work

Company: Ngm biopharmaceuticals Sep 2019 Position: Preclinical study coordinator

Education

Degree: Bachelors, Bachelor of Science School / High School: Uc Irvine 2011 to 2015 Specialities: Chemical Engineering

Skills

Microsoft Office • Powerpoint • Data Analysis • Laboratory Skills • Time Management • Python • Ir Spectroscopy • Mass Spectrometry • Microsoft Excel • Pcr • Bacterial Cell Culture • Mammalian Cell Culture • Agarose Gel Electrophoresis • Dna Extraction • Dna Replication • Sequence Analysis

Interests

Hands on Laboratory Experiments • Basketball • Learning New Technologies • Fishing • Health

Industries

Chemicals

Resumes

Resumes

Kyle Tsukamoto Photo 1

Preclinical Study Coordinator

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Location:
185 south Broad St, Pawcatuck, CT 06379
Industry:
Chemicals
Work:
Ngm Biopharmaceuticals
Preclinical Study Coordinator

Sri International
Biotechnician I

Stanford Institute For Stem Cell Biology and Regenerative Medicine Jun 2014 - Sep 2014
Summer Intern

Santo Market Jun 2010 - Jul 2010
Clerk

Jr Youth Buddhist Association 2009 - 2010
Fundraising Coordinator
Education:
Uc Irvine 2011 - 2015
Bachelors, Bachelor of Science, Chemical Engineering
Archbishop Mitty High School 2007 - 2011
Skills:
Microsoft Office
Powerpoint
Data Analysis
Laboratory Skills
Time Management
Python
Ir Spectroscopy
Mass Spectrometry
Microsoft Excel
Pcr
Bacterial Cell Culture
Mammalian Cell Culture
Agarose Gel Electrophoresis
Dna Extraction
Dna Replication
Sequence Analysis
Interests:
Hands on Laboratory Experiments
Basketball
Learning New Technologies
Fishing
Health

Publications

Us Patents

Load/Store Instruction Control Circuit Of Microprocessor And Load/Store Instruction Control Method

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US Patent:
6360298, Mar 19, 2002
Filed:
Feb 10, 2000
Appl. No.:
09/502550
Inventors:
Takeki Osanai - Ebina, JP
Johnny K. Szeto - San Jose CA
Kyle Tsukamoto - Santa Clara CA
Assignee:
Kabushiki Kaisha Toshiba
International Classification:
G06F 1200
US Classification:
711133, 24118, 24126, 24134, 24137, 24141, 24143
Abstract:
A load/store instruction control method of a microprocessor according to the present invention has a feature as follows. The circuit implements non-blocking cache which does not allow a pipeline process of a microprocessor to stop even if a cache miss by load/store instructions occurs. When the load instruction for a no-write allocate area directly storing a store-data to a lower layer memory in a cache hierarchy at time of a cache-miss initiates the cache-miss, and a subsequent store instruction initiates the cache-miss for the same cache line as that of the preceding load instruction, during a refill process of the DCACHE by the preceding load instruction or after the refill process, the store-data by the subsequent store instruction is stored to a corresponding cache line. Consequently, unconformity of data such as only the lower layer memory in the cache hierarchy holds a new data and only the DCACHE holds an old data does not occur.
Kyle S Tsukamoto from San Jose, CA, age ~66 Get Report