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Kyehyung Lee

from Austin, TX
Age ~57
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Also known as:
Kyehung Lee, Kyehyung Le, Hyung Lee Kye, Lee Kyehyung
Related to:
Tony Mayorga, 47Caroline M Mayorga, 56Ian Lee, 27Joong Lee, 56Jung W Kim, 53Lee YoungSohee LeeSeungjoon Lee, 31Changsun S Lee, 58Jimmy LeeSungchul Lee, 53Chang S Lee, 58Heung Kyu Lee, 52Jung W Kim, 59Yunhee Lee, 45Jae B Kim, 58Eunju Lee, 36Songam Lee
Connected to:
Aarron Lee, 39Ada P Lee, 66Adam Y Lee, 63Adrienna V Lee, 57Aekyung P Lee, 66Aeron C Lee, 48Ahmed F Lee, 57Ahran Lee, 38Ahrom A Lee, 37Aiesha M Lee, 40

Kyehyung Lee Phones & Addresses

  • Austin, TX
  • Irvine, CA
  • Corvallis, OR

Resumes

Resumes

Kyehyung Lee Photo 1

Analog Design Engineer

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Cirrus Logic
Analog Design Engineer
Kyehyung Lee Photo 2

Kyehyung Lee

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Publications

Us Patents

Programmable High-Resolution Timing Jitter Injectors High-Resolution Timing Jitter Injectors

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US Patent:
7348821, Mar 25, 2008
Filed:
Sep 22, 2004
Appl. No.:
10/946709
Inventors:
Jianping Xu - Portland OR, US
KyeHyung Lee - Corvallis OR, US
Fabrice Paillet - Hillsboro OR, US
David Rennie - Etobicoke, CA
Tanay Karnik - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03H 11/26
US Classification:
327276, 327263, 327287
Abstract:
A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

Noise-Shaped Scrambler For Reduced Out-Of-Band Common-Mode Interference

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US Patent:
7952508, May 31, 2011
Filed:
Sep 2, 2009
Appl. No.:
12/553004
Inventors:
Lorenzo Crespi - Costa Mesa CA, US
Ketan B Patel - Lake Forest CA, US
Kyehyung Lee - Irvine CA, US
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H03M 1/66
US Classification:
341152, 341 53
Abstract:
Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

Interpolation Delay Cell For 2Ps Resolution Jitter Injector In Optical Link Transceiver

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US Patent:
20050140412, Jun 30, 2005
Filed:
Dec 31, 2003
Appl. No.:
10/748300
Inventors:
KyeHyung Lee - Corvallis OR, US
Jianping Xu - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Tanay Karnik - Portland OR, US
International Classification:
H03H011/26
US Classification:
327261000
Abstract:
An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.

Current-Mode Sample And Hold For Dead Time Control Of Switched Mode Regulators

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US Patent:
20130154714, Jun 20, 2013
Filed:
Dec 19, 2012
Appl. No.:
13/719577
Inventors:
Kyehyung Lee - Irvine CA, US
Assignee:
CONEXANT SYSTEMS, INC. - Newport Beach CA
International Classification:
H03K 17/56
US Classification:
327362
Abstract:
A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.

Low Power Current Comparator For Switched Mode Regulator

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US Patent:
20130200872, Aug 8, 2013
Filed:
Jan 31, 2013
Appl. No.:
13/755575
Inventors:
Brian W. Friend - Carlsbad CA, US
Kyehyung Lee - Irvine CA, US
International Classification:
G05F 1/10
US Classification:
323284, 323282
Abstract:
A current comparator comprising a first NMOS transistor having a drain coupled to V, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to Vand a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to V, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Digital Pulse-Width Modulation (Pwm) Modulator With Dynamically Switchable Code Set For Reduced Total Harmonic Distortion And Noise (Thdn)

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US Patent:
20220247389, Aug 4, 2022
Filed:
Jan 29, 2021
Appl. No.:
17/162950
Inventors:
- Edinburgh, GB
Rahul Singh - Austin TX, US
Paul Astrachan - Austin TX, US
Kyehyung Lee - Austin TX, US
International Classification:
H03K 3/017
H03M 3/00
H04R 3/00
Abstract:
A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Pwm Modulator Having Quantizer Calibratable For Multi-Non-Ideal Gain-Affecting Characteristics

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US Patent:
20210044285, Feb 11, 2021
Filed:
Aug 18, 2020
Appl. No.:
16/996779
Inventors:
- Edinburgh, GB
Anuradha Parsi - Austin TX, US
Kyehyung Lee - Austin TX, US
John L. Melanson - Austin TX, US
International Classification:
H03K 7/08
H03K 4/06
H03K 4/56
H03F 3/217
H03F 3/185
H03M 3/00
Abstract:
A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Pwm Modulator Having Quantizer With Controllable Analog Gain And Calibratable For Multi-Non-Ideal Gain-Affecting Characteristics

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US Patent:
20200119702, Apr 16, 2020
Filed:
Oct 18, 2018
Appl. No.:
16/163766
Inventors:
- Edinburgh, GB
ANURADHA PARSI - Austin TX, US
KYEHYUNG LEE - Austin TX, US
JOHN L. MELANSON - Austin TX, US
International Classification:
H03F 3/185
H03F 3/217
H03M 3/00
Abstract:
A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
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Kyehyung Lee from Austin, TX, age ~57 Get Report