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Kurt K Sakamoto

from Fairborn, OH
Age ~63
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Also known as:
Dale Sakamoto
Related to:
Carl M Sakamoto, 80William Andrew Witte, 73
Connected to:
Ayako Sakamoto, 58Carol D Sakamoto, 73Daryle K Sakamoto, 63Donald D Sakamoto, 73Eiji Sakamoto, 39Erin E Sakamoto, 41George J Sakamoto, 91Hidemi Sakamoto, 73Hoshio E Sakamoto, 47James R Sakamoto, 75

Kurt Sakamoto Phones & Addresses

  • Fairborn, OH
  • Chandler, AZ
  • Gilbert, AZ
  • Mesa, AZ

Work

Company: The design knowledge company Oct 2018 Position: Senior analog design engineer

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: University of Hawaii at Manoa

Skills

Analog Circuit Design • Ic • Rf Design • Integrated Circuit Design • Rf • Semiconductors • Analog • Wireless • Asic • Cmos • Mixed Signal • Circuit Design • Mobile Communications • Simulations • Soc • Testing • Embedded Systems • Software Development • Application Specific Integrated Circuits • Integrated Circuits • Radio Frequency • Wireless Technologies

Industries

Defense & Space

Resumes

Resumes

Kurt Sakamoto Photo 1

Senior Analog Design Engineer

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Location:
307 Carpenter Dr, Fairborn, OH 45324
Industry:
Defense & Space
Work:
The Design Knowledge Company
Senior Analog Design Engineer
Intel Corporation Jul 2013 - Oct 2018
Rf and Analog Design Engineer
Fujitsu Apr 2009 - Jul 2013
Rf Design Engineer
Freescale Semiconductor Oct 2006 - Apr 2009
Rf Design Engineer
On Semiconductor 1999 - 2006
Senior Principal Design Engineer
Education:
University of Hawaii at Manoa
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Analog Circuit Design
Ic
Rf Design
Integrated Circuit Design
Rf
Semiconductors
Analog
Wireless
Asic
Cmos
Mixed Signal
Circuit Design
Mobile Communications
Simulations
Soc
Testing
Embedded Systems
Software Development
Application Specific Integrated Circuits
Integrated Circuits
Radio Frequency
Wireless Technologies

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kurt Sakamoto
Professional Engineer
ON Semiconductor
Semiconductors · Mfg Semiconductors/Devices Electric Measuring Instrument & Home Audio/Video Equipment · Mfg Semiconductors/Dvcs Engineering Services Elec Measuring Instr & Home Audio/Video Eqp · Mfg Semiconductors/Dvcselec Measuring Instr & Home Audio/Video Eqp · Nonclassifiable Establishments · Semiconductors and Related Devices · Semiconductor Devices (Manufac
5005 E Mcdowell Rd, Phoenix, AZ 85008
5005 E Mcdowell Rd Ms C 250, Phoenix, AZ 85008
1209 Orange St, Wilmington, DE 19801
(602) 244-6600, (602) 244-6071, (602) 244-7160, (602) 244-7005

Publications

Us Patents

Method Of Manufacturing A Semiconductor Component And Semiconductor Component Thereof

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US Patent:
6387768, May 14, 2002
Filed:
Aug 29, 2000
Appl. No.:
09/649782
Inventors:
Kurt Sakamoto - Chandler AZ
Assignee:
Semiconductor Components Industries LLC - Phoenix AZ
International Classification:
H01L 21331
US Classification:
438367, 433309
Abstract:
A method of manufacturing a semiconductor component includes providing a substrate ( ), an electrically insulative layer ( or ) over the substrate, and an electrically conductive layer ( ) over the electrically insulative layer. A hole ( ) is etched into a portion ( ) of the electrically conductive layer and into a portion of the electrically insulative layer. Another electrically conductive layer ( ) is deposited in the hole, and the two electrically conductive layers are etched to leave a portion ( ) of the second electrically conductive layer in the hole. Then, an additional electrically conductive layer ( ) is grown over the substrate and over the portion of the second electrically conductive layer.

Optically Sensitive Device And Method

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US Patent:
58863745, Mar 23, 1999
Filed:
Jan 5, 1998
Appl. No.:
/002801
Inventors:
Kurt K. Sakamoto - Chandler AZ
Peter J. Zdebel - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 31062
H01L 31113
H01L 31075
H01L 31105
US Classification:
257292
Abstract:
A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).

Integrated Circuit Capacitor Having A Conductive Trench

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US Patent:
55746217, Nov 12, 1996
Filed:
Mar 27, 1995
Appl. No.:
8/411194
Inventors:
Kurt K. Sakamoto - Chandler AZ
Neil T. Tracht - Mesa AZ
Robert A. Pryor - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01G 406
H01L 27108
US Classification:
3613211
Abstract:
A capacitor (58) for an integrated circuit having a conductive trench (50), disposed below a bottom electrode layer (52), that electrically connects the bottom electrode layer to a semiconductor substrate (14, 16). The conductive trench eliminates the need for a top-side contact to the bottom electrode layer. The semiconductor substrate is, for example, connected to ground.

High Frequency Bipolar Transistor And Method Of Forming The Same

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US Patent:
59659300, Oct 12, 1999
Filed:
Nov 4, 1997
Appl. No.:
8/964001
Inventors:
Kurt K. Sakamoto - Chandler AZ
Peter J. Zdebel - Mesa AZ
Michael G. Lincoln - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 29732
US Classification:
257584
Abstract:
A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.
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Kurt K Sakamoto from Fairborn, OH, age ~63 Get Report