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Kurt N Kimber

from Minneapolis, MN
Age ~70
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Also known as:
Newton Kimber Kruth, Kimber K Wyatt
Phone and address:
4811 35Th Ave S, Minneapolis, MN 55417
(612) 729-4759
Related to:
Jack KlineSamuel J Kimber, 46Clay O Kimber, 48K WyattAngela J Wyatt, 67Kimberly A Eicher, 46Patricia A Kline, 75Charles J Kline, 78Kimber K WyattKathleen Wyatt
Connected to:
Anne W Kimber, 67Brad Kimber, 38Bret Kimber, 97Carey D Kimber, 38Carol S Kimber, 76Chivas S Kimber, 40Cory E Kimber, 54Donna G Kimber, 66Doug M Kimber, 50Erin S Kimber, 32

Kurt Kimber Phones & Addresses

  • 4811 35Th Ave S, Minneapolis, MN 55417 (612) 729-4759

Work

Company: Micron technology May 2018 Position: Analog ic designer

Education

Degree: Masters School / High School: University of Minnesota 1988 to 1990 Specialities: Electrical Engineering

Skills

Power Electronics Design • Power Electronics • Power Supplies • Power Management • Ic • Integrated Circuit Design • Circuit Design • Analog Circuit Design • Mixed Signal • Asic • Analog • Cmos • Hardware Architecture • Debugging • Eda • Cadence Analog Artist • Cadence Virtuoso • Semiconductor Industry • Semiconductors • Cadence

Interests

Renewable Energy • Clean Energy

Industries

Semiconductors

Resumes

Resumes

Kurt Kimber Photo 1

Analog Ic Designer

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Location:
Minneapolis, MN
Industry:
Semiconductors
Work:
Micron Technology
Analog Ic Designer
Starkey Hearing Technologies Aug 2016 - Nov 2017
Senior Ic Engineer Ii
Allegro Microsystems, Llc Jan 1, 2012 - Jun 2016
Principal Design Engineer
Sanken Electric Oct 2006 - Dec 2011
Consulting Design Engineer
Polar Semiconductor, Llc Jun 2000 - Sep 2006
Consulting Design Engineer
Education:
University of Minnesota 1988 - 1990
Masters, Electrical Engineering University of Minnesota 1984 - 1988
Bachelors, Electrical Engineering
Skills:
Power Electronics Design
Power Electronics
Power Supplies
Power Management
Ic
Integrated Circuit Design
Circuit Design
Analog Circuit Design
Mixed Signal
Asic
Analog
Cmos
Hardware Architecture
Debugging
Eda
Cadence Analog Artist
Cadence Virtuoso
Semiconductor Industry
Semiconductors
Cadence
Interests:
Renewable Energy
Clean Energy

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kurt Kimber
Principal
The Ancia Quartet Inc
Entertainer/Entertainment Group
4319 Longfellow Ave, Minneapolis, MN 55407

Publications

Us Patents

System And Method For Dynamic Esd Protection

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US Patent:
6898061, May 24, 2005
Filed:
Jul 10, 2003
Appl. No.:
10/616801
Inventors:
Kurt Kimber - Minneapolis MN, US
David Litfin - Houlton WI, US
Assignee:
PolarFab, LLC - Bloomington MN
International Classification:
H02H009/00
US Classification:
361 56
Abstract:
A system and method for dynamically protecting a vulnerable device from an ESD event includes an ESD event sensor and a breakdown voltage adjustment circuit. The ESD event sensor detects an ESD event and provides a signal to the breakdown voltage adjustment circuit indicating that an ESD event has occurred. The breakdown voltage adjustment circuit receives the signal from the ESD event sensor and adjusts the breakdown voltage of the vulnerable device during the ESD event.

Bipolar Junction Transistor Antifuse

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US Patent:
7071533, Jul 4, 2006
Filed:
Feb 4, 2005
Appl. No.:
11/051396
Inventors:
Kurt N. Kimber - Minneapolis MN, US
David D. Litfin - Houlton WI, US
Joseph Burkhardt - Minneapolis MN, US
Steven L. Kosier - Lakeville MN, US
Assignee:
Polar Semiconductor, Inc. - Bloomington MN
International Classification:
H01L 29/00
US Classification:
257529, 257565
Abstract:
An antifuse device is constructed from a bipolar junction transistor (BJT). The BJT includes a collector, a base, and an emitter. In one embodiment the BJT is formed inherently within a field effect transistor (FET), including a first doped region, a second doped region, a gate, and a body region. The collector of the BJT is realized by the first doped region of the FET, the emitter of the BJT is realized by the second doped region of the FET, and the base of the BJT is realized by the body region. A high resistance path exists between the collector and the base. A first input voltage is connected to the collector and a second input voltage is connected to the base. A switch connects the emitter to a fixed potential when the switch is closed. The antifuse device is programmed by closing the switch and allowing the first input voltage and the second input voltage to create a large current from the collector to the emitter, through the base, such that the high resistance path between the collector and the base is converted to a permanent low resistance path.

Over-Current Protection Device For A Switched-Mode Power Supply

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US Patent:
7817391, Oct 19, 2010
Filed:
Apr 26, 2007
Appl. No.:
11/796097
Inventors:
Kurt N. Kimber - Minneapolis MN, US
Assignee:
Polar Semiconductor, Inc. - Bloomington MN
International Classification:
H02H 3/00
US Classification:
361 87, 361 931, 361100, 361154, 323282
Abstract:
An over-current protection device for use in a switched mode power supply prevents over-current conditions caused by short-circuits faults. The over-current protection device monitors a current in the switched mode power supply, and in particular, determines a peak current value associated with the monitored current. The monitored current is compared to a reference value to determine whether an over-current condition exists. If an over-current condition is detected, then the over-current protection device modifies the ‘off’ time of the switched mode power supply based on the determined peak current value.

Power Supply For Floating Loads

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US Patent:
20100295472, Nov 25, 2010
Filed:
May 6, 2010
Appl. No.:
12/800057
Inventors:
Josh Wibben - Eden Prairie MN, US
Robert Schuelke - Lakeville MN, US
Kurt Kimber - Minneapolis MN, US
Assignee:
Polar Semiconductor, Inc. - Bloomington MN
International Classification:
H05B 41/36
H02J 4/00
US Classification:
315294, 307 31
Abstract:
A power supply includes a current supply, a plurality of output channels, and a controller. Each of the output channels has a load and a channel switch with a reference voltage. All of the channel switches are referenced to the same reference voltage.

Simplified Control Of Color Temperature For General Purpose Lighting

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US Patent:
20110115407, May 19, 2011
Filed:
Nov 15, 2010
Appl. No.:
12/946421
Inventors:
Josh Wibben - New Brighton MN, US
Kurt Kimber - Minneapolis MN, US
Crispin Metzler - Hastings MN, US
Assignee:
POLAR SEMICONDUCTOR, INC. - Bloomington MN
International Classification:
H05B 37/02
US Classification:
315294
Abstract:
A lighting system includes at least first and second light sources providing first and second colors of light. Control circuitry is operatively coupled to the first and second light sources, and is configured to control the first and second light sources relative to one another to provide a color point that is linearly controlled to approximate a non-linear target lighting behavior in the CIE 1931 color space.

Anti-Snapback Circuitry For Metal Oxide Semiconductor (Mos) Transistor

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US Patent:
20130292770, Nov 7, 2013
Filed:
May 4, 2012
Appl. No.:
13/464422
Inventors:
Kurt Kimber - Minneapolis MN, US
David Litfin - Houlton WI, US
Assignee:
POLAR SEMICONDUCTOR, INC. - Bloomington MN
International Classification:
H01L 27/06
US Classification:
257355, 257E27016
Abstract:
A circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event. The circuit includes at least one active device or capacitance-providing element connected to the gate of the protected MOS device, configured to pull down or hold down the voltage at the gate of the protected MOS device when the ESD event occurs.

High Performance Maximum And Minimum Circuit

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US Patent:
58251685, Oct 20, 1998
Filed:
Jun 13, 1997
Appl. No.:
8/874762
Inventors:
Kurt N. Kimber - Minneapolis MN
Assignee:
VTC, Inc. - Bloomington MN
International Classification:
G05F 316
US Classification:
323315
Abstract:
The present invention is a circuit for producing an output voltage as a function of a first input voltage and a second input voltage. The circuit includes a first emitter-coupled transistor pair for receiving the first and second input voltages. The circuit further includes a compensation circuit coupled to receive the first and the second input voltage signals. The compensation circuit generates a compensation current that is at least partially based on a relative difference between the first and the second input voltage signals. The compensation circuit is coupled to the first emitter-coupled transistor pair such that the compensation circuit provides the compensation current to the first emitter-coupled transistor pair. The output signal is representative of either the first or the second input voltage.

Switching Regulator Control Circuit

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US Patent:
20150340950, Nov 26, 2015
Filed:
Feb 12, 2015
Appl. No.:
14/620656
Inventors:
- Worcester MA, US
Kurt Kimber - Minneapolis MN, US
Peter Tod - Edinburgh, GB
Assignee:
ALLEGRO MICROSYSTEMS, LLC - Worcester MA
International Classification:
H02M 3/158
Abstract:
A switching regulator control circuit includes a circuit configured to generate a control signal to control conduction of the regulator switch in response to a reference signal that is ramped to control a rate of change of the regulated output of the regulator and the control signal is gated in response to a PWM signal.
Control profile
Kurt N Kimber from Minneapolis, MN, age ~70 Get Report