Search

Kumar Ganapathy

from Albuquerque, NM
Get Report
Also known as:
Kumer Ganapathy, Ganapathy Kumar
Related to:
Muthusamy Kumar, 53
Connected to:
Anjali B Ganapathy, 56Jayalakshmi Ganapathi, 52Krishna P Ganapathi, 32Mala Ganapathy, 67Narayanan Ganapathy, 83Neeraj K Ganapathy, 36Rajasekar Ganapathi, 40Shwetha Ganapathy, 37Srikanth Ganapathy, 54Swaroopa R Ganapathy, 49

Kumar Ganapathy Phones & Addresses

  • Albuquerque, NM
  • Milpitas, CA
  • Chandler, AZ
  • Cookeville, TN
  • Lancaster, PA

Work

Company: Lsg sky chefs Position: Materials manager

Education

School / High School: Pepperdine University- Malibu, CA Jan 2001 Specialities: Master of Science in Technology Management

Resumes

Resumes

Kumar Ganapathy Photo 1

Kumar Ganapathy Cupertino, CA

View page
Work:
LSG Sky Chefs

Materials Manager
Kasa Anlagen
Chennai, Tamil Nadu
Dec 2011 to Dec 2011
Supply Chain Specialist (contract)
AB Sciex, LLC
Foster City, CA
Aug 2010 to Jun 2011
Master Planner
The Galleon Group
Menlo Park, CA
Jun 2007 to Dec 2009
Research Associate
@Road/Trimble
Fremont, CA
Oct 1999 to Apr 2007
Supply Chain Program Manager
Atmel Corporation
San Jose, CA
Jun 1994 to Sep 1999
Production Control Planner
Infoex International Inc
San Francisco, CA
Jan 1992 to Jun 1994
Sales Manager
Education:
Pepperdine University
Malibu, CA
Jan 2001 to Jan 2002
Master of Science in Technology Management
University of San Francisco
San Francisco, CA
Jan 1987 to Jan 1990
Bachelor of Science in Business Administration

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kumar N. Ganapathy
President, Chief Operating Officer
VIRIDENT SYSTEMS, INC
Business Services · Commercial Physical Research
3355 Michelson Dr SUITE 100, Irvine, CA 92612
500 Yosemite Dr, Milpitas, CA 95035
(408) 945-9345
Kumar Ganapathy
Kg Property Investments LLC
Buying and Selling Distressed Residentia
21852 Monte Ct, Cupertino, CA 95014

Publications

Us Patents

Method And Apparatus For Instruction Set Architecture To Perform Primary And Shadow Digital Signal Processing Sub-Instructions Simultaneously

View page
US Patent:
6408376, Jun 18, 2002
Filed:
Aug 30, 2000
Appl. No.:
09/652100
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Dublin CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 922
US Classification:
712 36, 712 35, 712 41, 712215, 712228, 712227, 712245, 709108
Abstract:
Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. In one embodiment, a single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. The DSP operations, in one embodiment, include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX), and a no operation instruction (NOP). Each signal processing unit includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. Control logic is utilized to control shadow selectors of each signal processing unit to select delayed data (specified by the shadow DSP sub-instruction) for use by the shadows stages of the signal processing units.

Dyadic Operations Instruction Processor With Configurable Functional Blocks

View page
US Patent:
6446195, Sep 3, 2002
Filed:
Jan 31, 2000
Appl. No.:
09/494608
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9302
US Classification:
712221, 708501, 708523, 712 24, 712 35
Abstract:
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (âopcodeâ). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Processors With Data Typer And Aligner Selectively Coupling Data Bits Of Data Buses To Adder And Multiplier Functional Blocks To Execute Instructions With Flexible Data Types

View page
US Patent:
6557096, Apr 29, 2003
Filed:
Aug 31, 2000
Appl. No.:
09/652556
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Dublin CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9302
US Classification:
712221, 708513, 708518, 712210, 712300
Abstract:
A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.

Method And Apparatus For Loop Buffering Digital Signal Processing Instructions

View page
US Patent:
6598155, Jul 22, 2003
Filed:
Jan 31, 2000
Appl. No.:
09/494609
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Fremont CA
Kenneth Malich - Norco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
712241, 711110
Abstract:
A loop buffer for storing and holding instructions executed within loops for digital signal processing. Control logic detects the beginning and ending of a loop to signal the loop buffer control logic to start instruction execution in a cyclical fashion using the instructions stored within the loop buffer. After completion of the required number of loops, the instructions in the loop buffer are overwritten with new instructions until the next loop is to be processed. The loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.

Dyadic Dsp Instructions For Digital Signal Processors

View page
US Patent:
6631461, Oct 7, 2003
Filed:
Aug 8, 2002
Appl. No.:
10/216575
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9302
US Classification:
712221, 708501, 708523, 712 24, 712 35
Abstract:
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (âopcodeâ). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Dyadic Dsp Instruction Processor With Main And Sub-Operation Functional Blocks Selected From Each Set Of Multiplier And Adder

View page
US Patent:
6643768, Nov 4, 2003
Filed:
Aug 9, 2002
Appl. No.:
10/216044
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9302
US Classification:
712221, 708501, 708523, 712 24, 712 35
Abstract:
A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.

Selectively Multiplexing Memory Coupling Global Bus Data Bits To Narrower Functional Unit Coupling Local Bus

View page
US Patent:
6732203, May 4, 2004
Filed:
Mar 29, 2002
Appl. No.:
10/109826
Inventors:
Ruban Kanapathippillai - Dublin CA
Kumar Ganapathy - Palo Alto CA
Thu Nguyen - Saratoga CA
Siva Venkatraman - San Jose CA
Manoj Mehta - Laguna Hills CA
Kenneth Malich - Norco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1338
US Classification:
710 66, 710307, 712 33
Abstract:
In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.

Method And Apparatus For Instruction Set Architecture To Perform Primary And Shadow Digital Signal Processing Sub-Instructions Simultaneously

View page
US Patent:
6748516, Jun 8, 2004
Filed:
Jan 29, 2002
Appl. No.:
10/059698
Inventors:
Kumar Ganapathy - Mountain View CA
Ruban Kanapathipillai - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1576
US Classification:
712 35, 712 36, 712221, 712227, 712225, 712226, 712213, 712 25, 708508, 708603
Abstract:
Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.
Control profile
Kumar Ganapathy from Albuquerque, NM Get Report