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Klas O Lilja

from Pleasanton, CA
Age ~64
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Also known as:
Lilja Klas, Klas A
Phone and address:
3512 Kamp Ct, Pleasanton, CA 94588
(925) 485-4552
Related to:
Cathrine M Lilja, 24Caroline L Lilja, 29Marianne Lilja, 62
Connected to:
Andrew F Lilja, 33Birgitta G Lilja, 89Dean L Lilja, 67Duane F Lilja, 92Elisabeth T Lilja, 40Gabriel Lilja, 31Sam A Lilja, 49Ann M Lilje, 87Chris M Lilje, 70Dean M Liljeberg, 56

Klas Lilja Phones & Addresses

  • 3512 Kamp Ct, Pleasanton, CA 94588 (925) 485-4552 (925) 399-5456
  • Dublin, CA
  • San Jose, CA
  • Sunnyvale, CA
  • 5050 Hacienda Dr APT 427, Dublin, CA 94568

Work

Position: Medical Professional

Education

Degree: High school graduate or higher

Resumes

Resumes

Klas Lilja Photo 1

Founder, Chief Executive Officer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Robust Chip Inc.
Founder, Chief Executive Officer
Ise Integrated Systems Engineering Dec 1999 - 2002
Chief Executive Officer
Avant Corporation 1996 - 1999
Head of Tcad
Education:
Chalmers University of Technology 1981 - 1986
Eth Zürich
Doctorates, Doctor of Philosophy, Physics
Skills:
Semiconductors
Ic
Start Ups
Simulations
Physics
Asic
Electronics
R&D
Cmos
Eda
Embedded Systems
Silicon
C++
Characterization
Sensors
Product Management
Entrepreneurship
Testing
Product Development
Tcad
Klas Lilja Photo 2

Klas Lilja

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Klas Lilja
President
Chip Robust Inc
Electronic Design Services
7901 Stoneridge Dr, Pleasanton, CA 94588
(925) 425-0820
Klas O. Lilja
President
Robust Chip Inc.
Semiconductors
7901 Stoneridge Dr, Pleasanton, CA 94568
5820 Stoneridge Mall Rd, Pleasanton, CA 94588
(925) 425-0820
Klas O. Lilja
Mixed Technology Associates, LLC
Electronic Design Automation Software An
5820 Stoneridge Mall Rd, Pleasanton, CA 94588

Publications

Us Patents

Layout Method For Soft-Error Hard Electronics, And Radiation Hardened Logic Cell

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US Patent:
8468484, Jun 18, 2013
Filed:
Mar 20, 2012
Appl. No.:
13/425231
Inventors:
Klas Olof Lilja - Dublin CA, US
Assignee:
Klas Olof Lilja - Dublin CA
International Classification:
G06F 17/50
US Classification:
716119, 716122
Abstract:
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (. ltoreq. 90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Soft Error Hard Electronic Circuit And Layout

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US Patent:
8495550, Jul 23, 2013
Filed:
Apr 19, 2010
Appl. No.:
12/763139
Inventors:
Klas Olof Lilja - Pleasanton CA, US
International Classification:
G06F 17/50
G06F 9/455
H03K 19/003
H03K 19/173
US Classification:
716130, 716101, 716104, 716106, 716112, 716119, 716132, 716 55, 326 10, 326 46, 326 47
Abstract:
This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.

Layout Method For Soft-Error Hard Electronics, And Radiation Hardened Logic Cell

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US Patent:
8566770, Oct 22, 2013
Filed:
Oct 19, 2011
Appl. No.:
13/277135
Inventors:
Klas Olof Lilja - Pleasanton CA, US
International Classification:
G06F 17/50
H03K 19/003
H03K 19/007
US Classification:
716119, 716106, 716111, 716120, 716132, 716136, 716139, 716 55, 326 9, 326 12, 326 14
Abstract:
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (. ltoreq. 90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Method, And Extensions, To Couple Substrate Effects And Compact Model Circuit Simulation For Efficient Simulation Of Semiconductor Devices And Circuit

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US Patent:
20090044158, Feb 12, 2009
Filed:
Apr 11, 2008
Appl. No.:
12/101808
Inventors:
Klas Olof Lilja - Pleasanton CA, US
International Classification:
G06F 17/50
US Classification:
716 5
Abstract:
This invention comprises a new method to couple simulation of electronics circuits (using compact models) with simulation of physical effects which require a PDE (partial differential equation) based simulation, for semiconductor MOSFET based devices and circuits. In particular the method can be used to capture high injection substrate effects such as single event transients (SET), latch-up, ESD, or thermal effects. Bipolar substrate effects are handled correctly and completely with this algorithm. The method extends the applicability of technology CAD (TCAD) to multiple devices.

Layout Method For Soft-Error Hard Electronics, And Radiation Hardened Logic Cell

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US Patent:
20090184733, Jul 23, 2009
Filed:
Jan 15, 2009
Appl. No.:
12/354655
Inventors:
Klas Olof Lilja - Pleasanton CA, US
International Classification:
H03K 19/00
G06F 17/50
US Classification:
326101, 716 12
Abstract:
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (≦90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Layout Method For Soft-Error Hard Electronics, And Radiation Hardened Logic Cell

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US Patent:
20130038348, Feb 14, 2013
Filed:
May 3, 2012
Appl. No.:
13/463688
Inventors:
Klas Olof Lilja - Dublin CA, US
International Classification:
H03K 19/173
US Classification:
326 46
Abstract:
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Soft Error Hard Electronics Layout Arrangement And Logic Cells

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US Patent:
20130162293, Jun 27, 2013
Filed:
Dec 3, 2012
Appl. No.:
13/692800
Inventors:
ROBUST CHIP INC. - Pleasanton CA, US
Klas Olof Lilja - Pleasanton CA, US
Assignee:
ROBUST CHIP INC. - Pleasanton CA
International Classification:
H03K 19/21
G06F 17/50
H03K 19/20
US Classification:
326 54, 326 55, 326113, 716103, 716121
Abstract:
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.

Layout Method For Soft-Error Hard Electronics, And Radiation Hardened Logic Cell

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US Patent:
20130227499, Aug 29, 2013
Filed:
May 3, 2012
Appl. No.:
13/463706
Inventors:
Klas Olof Lilja - Dublin CA, US
International Classification:
G06F 17/50
US Classification:
716 55
Abstract:
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Isbn (Books And Publications)

Analysis and Numerical Simulation of Current Filamentation in Power Semiconductor Devices

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Author

Klas Lilja

ISBN #

3891916221

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Klas O Lilja from Pleasanton, CA, age ~64 Get Report