Kirk H Hwang

7467346, Dec 16, 2008

Aug 18, 2005

11/207474

Martin Hassner - Mountain View CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands, B.V. - Amsterdam

H03M 13/00

714781, 714784

Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, a plurality of modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

7716268, May 11, 2010

Mar 4, 2005

11/072211

Jeffrey J. Dobbek - Morgan Hill CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

G06F 7/38
G06F 1/02

708523, 708270

A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data address pointers for evaluating a polynomial, to load loading a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.

7743311, Jun 22, 2010

Jan 26, 2006

11/341230

Martin Hassner - Mountain View CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands, B.V. - Amsterdam

H03M 13/00

714785

A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.

7774679, Aug 10, 2010

Feb 14, 2005

11/058596

Martin Hassner - Mountain View CA, US
Vipul Srivastava - San Jose CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

H03M 13/00

714758, 714781, 714 48, 714799, 714E11001, 714E11002, 714E11003, 714E11049, 708492

Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(2), GF(2) is extended to a first quadratic extension GF(2), and GF(2) is extended to a second quadratic extension GF(2). In the 10-bit embodiment, the base field GF(2) is first extended to GF(2), and GF(2) is extended to a quadratic extension GF(2). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x+x+K, where K is an element of the ground field whose absolute trace equals 1.

8014095, Sep 6, 2011

Dec 28, 2007

12/005963

Kirk Hwang - Palo Alto CA, US
Michael A. Moser - San Jose CA, US
Spencer W. Ng - San Jose CA, US

Hitachi Global Storage Technologies, Netherlands, B.V. - Amsterdam

G11B 5/09

360 48, 360 49

A magnetic disk for a hard disk drive comprising a plurality of physical sector sizes is disclosed. The magnetic disk includes a first sector size area physically formatted according to a first physical sector size and a second sector size area physically formatted according to a second physical sector size different from the first sector size by a multiple of the first sector size wherein the second sector size can be presented externally as multiple sectors of said first sector size.

8117248, Feb 14, 2012

Feb 28, 2005

11/067962

Jeffrey J. Dobbek - Morgan Hill CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

G06F 17/10

708300, 708271, 708303, 708309

A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

8201061, Jun 12, 2012

Nov 13, 2008

12/270737

Martin Hassner - Mountain View CA, US
Kirk Hwang - Palo Alto CA, US

Hitachi Global Storage Technologies Netherlands, B.V. - Amsterdam

H03M 13/00

714785, 714781

Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

8280941, Oct 2, 2012

Dec 19, 2007

12/004250

Jeffrey J. Dobbek - Morgan Hill CA, US
Kirk Hwang - Palo Alto CA, US

HGST Netherlands B.V. - Amsterdam

G06F 7/52
G06F 7/44
G06F 15/00

708625, 708503, 708603

A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.