Kimon W Michaels

7174521, Feb 6, 2007

Mar 10, 2005

11/078630

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

PDF Solutions, Inc. - San Jose CA

G06F 17/50

716 4, 703 2

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

7356800, Apr 8, 2008

Aug 10, 2006

11/503323

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

PDF Solutions, Inc. - San Jose CA

G06F 17/50

716 21, 716 4, 716 19

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

7373625, May 13, 2008

Aug 10, 2006

11/503433

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

PDF Solutions, Inc. - San Jose CA

G06F 17/50

716 4, 716 19, 716 21

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

7673262, Mar 2, 2010

May 13, 2008

12/119862

Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

PDF Solutions, Inc. - San Jose CA

G06F 17/50

716 4, 716 21

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

20030145292, Jul 31, 2003

Jul 18, 2002

10/200045

Brian Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph Davis - Allen TX, US
Purnendu Mozumder - Plano TX, US
Sherry Lee - San Jose CA, US
Larg Weiland - San Ramon CA, US
Dennis Ciplickas - San Jose CA, US
David Stashower - Los Gatos CA, US

G06F017/50

716/004000

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

20170178981, Jun 22, 2017

Apr 4, 2016

15/090256

- San Jose CA, US
Dennis Ciplickas - San Jose CA, US
Tomasz Brozek - Morgan Hill CA, US
Jeremy Cheng - San Jose CA, US
Simone Comensoli - Darfo Boario Terme, IT
Indranil De - Mountain View CA, US
Kelvin Doong - Hsinchu City, TW
Hans Eisenmann - Tutzing, DE
Timothy Fiscus - New Galilee PA, US
Jonathan Haigh - Pittsburgh PA, US
Christopher Hess - Belmont CA, US
John Kibarian - Los Altos Hills CA, US
Sherry Lee - Monte Sereno CA, US
Marci Liao - Santa Clara CA, US
Sheng-Che Lin - Hsinchu City, TW
Hideki Matsuhashi - Santa Clara CA, US
Kimon Michaels - Monte Sereno CA, US
Conor O'Sullivan - Campbell CA, US
Markus Rauscher - Munich, DE
Vyacheslav Rovner - Pittsburgh PA, US
Andrzej Strojwas - Pittsburgh PA, US
Marcin Strojwas - Pittsburgh PA, US
Carl Taylor - Pittsburgh PA, US
Rakesh Vallishayee - Dublin CA, US
Larg Weiland - Hollister CA, US
Nobuharu Yokoyama - Tokyo, JP

H01L 21/66

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

20150270181, Sep 24, 2015

Feb 3, 2015

14/612841

- San Jose CA, US
Dennis J. Ciplickas - San Jose CA, US
Stephen Lam - Freemont CA, US
Jonathan Haigh - Pittsburgh PA, US
Vyacheslav V. Rovner - Pittsburgh PA, US
Christopher Hess - Belmont CA, US
Tomasz W. Brozek - Morgan Hill CA, US
Andrzej J. Strojwas - Pittsburgh PA, US
Kelvin Doong - Zhubei City, TW
John K. Kibarian - Los Altos CA, US
Sherry F. Lee - Monte Sereno CA, US
Kimon W. Michaels - Monte Sereno CA, US
Marcin A. Strojwas - Pittsburgh PA, US
Conor O'Sullivan - Campbell CA, US
Mehul Jain - San Jose CA, US

H01L 21/66
G01R 31/26

Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.