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Kim Susanne Pierce

from Boise, ID
Age ~65
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Also known as:
Kim S Pierce, Kim S Wheldon
Related to:
Christopher J Pierce, 40Traci Wheldon, 62Maci Wheldon, 33Sally Wheldon, 29Steve Wheldon, 63
Connected to:
Adrieanna J Pierce, 65Ajani T Pierce, 45Akyra Pierce, 31Alayne S Pierce, 36Alexander S Pierce, 49Alexis C Pierce, 41Alexus L Pierce, 28Alison Pierce, 41Amilius M Pierce, 38Angel Pierce, 50

Kim Pierce Phones & Addresses

  • Boise, ID
  • Springfield, OR
  • Eagle, ID
  • 6790 W Foggy Bottom St, Boise, ID 83714 (208) 853-8944

Education

Degree: Associate degree or higher

Professional Records

Medicine Doctors

Kim Pierce Photo 1

Kim M. Pierce

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Specialties:
Internal Medicine
Work:
AHN Stone Quarry Internal Medicine
811 Cp Horne Rd Mezzanie Lvl, Pittsburgh, PA 15237
(412) 847-2626 (phone), (412) 847-2631 (fax)
Education:
Medical School
University of Pittsburgh School of Medicine
Graduated: 1998
Procedures:
Electrocardiogram (EKG or ECG)
Pulmonary Function Tests
Vaccine Administration
Conditions:
Acute Upper Respiratory Tract Infections
Anemia
Bronchial Asthma
Gastroesophageal Reflux Disease (GERD)
Hypertension (HTN)
Languages:
English
Description:
Dr. Pierce graduated from the University of Pittsburgh School of Medicine in 1998. She works in Pittsburgh, PA and specializes in Internal Medicine.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kim Pierce
REACH CRANE, LLC
Kim Pierce
pierce
Family Doctor

(412) 749-6839
Kim Eugene Pierce
Vice President,Director
PIERCE & SON TRUCKING, INC

Publications

Us Patents

Method And Apparatus For Storage Of Test Results Within An Integrated Circuit

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US Patent:
6365421, Apr 2, 2002
Filed:
Mar 20, 2000
Appl. No.:
09/531023
Inventors:
Brett Debenham - Meridian ID
Kim Pierce - Meridian ID
Douglas J. Cutter - Fort Collins CO
Kurt Beigel - Boise ID
Fan Ho - Sunnyvale CA
Patrick J. Mullarkey - Meridian ID
Dien Luong - Boise ID
Hua Zheng - Fremont CA
Michael Shore - Boise ID
Jeffrey P. Wright - Boise ID
Adrian E. Ong - Pleasanton CA
Todd A. Merritt - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2166
US Classification:
438 14, 438 10, 438 13, 438 18
Abstract:
An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

On-Chip Circuit And Method For Testing Memory Devices

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US Patent:
6536004, Mar 18, 2003
Filed:
Jan 23, 2001
Appl. No.:
09/769031
Inventors:
Kim M. Pierce - Meridian ID
Charles L. Ingalls - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 2900
US Classification:
714719, 365200, 365201
Abstract:
An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal.

Semiconductor Integrated Circuit Having Compression Circuitry For Compressing Test Data, And The Test System And Method For Utilizing The Semiconductor Integrated Circuit

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US Patent:
6546512, Apr 8, 2003
Filed:
Aug 27, 2001
Appl. No.:
09/940010
Inventors:
Roland Ochoa - Boise ID
Gregory L. Cowan - Boise ID
Kim M. Pierce - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 3128
US Classification:
714724, 324765
Abstract:
A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Semiconductor Integrated Circuit Having Compression Circuitry For Compressing Test Data, And The Test System For Utilizing The Semiconductor Integrated Circuit

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US Patent:
6665827, Dec 16, 2003
Filed:
Jan 14, 2003
Appl. No.:
10/342651
Inventors:
Roland Ochoa - Boise ID
Gregory L. Cowan - Boise ID
Kim M. Pierce - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01R 3128
US Classification:
714724, 324765
Abstract:
A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

On-Chip Circuit And Method For Testing Memory Devices

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US Patent:
61785326, Jan 23, 2001
Filed:
Jun 11, 1998
Appl. No.:
9/096279
Inventors:
Kim M. Pierce - Meridian ID
Charles L. Ingalls - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 2900
US Classification:
714718
Abstract:
An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal.

Self Current Limiting Antifuse Circuit

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US Patent:
56318626, May 20, 1997
Filed:
Mar 5, 1996
Appl. No.:
8/611419
Inventors:
Douglas J. Cutter - Boise ID
Kurt D. Beigel - Boise ID
Adrian E. Ong - Santa Clara CA
Fan Ho - Boise ID
Patrick J. Mullarkey - Meridian ID
Dien S. Luong - Boise ID
Brett Debenham - Meridian ID
Kim M. Pierce - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1716
US Classification:
365 96
Abstract:
An antifuse bank includes a bank of self-decoupling antifuse circuits. The antifuse circuits are programmed according to a pattern of address bits by blowing antifuses corresponding to bits of the address. The antifuses are blown by applying a high voltage across the antifuse. As each antifuse is blown, its resistance drops and current through the antifuse increases. The self-decoupling circuit detects the increased current flow and, when the antifuse resistance is sufficiently low, limits current flow through the antifuse. The antifuse thus does not load the high voltage source as other antifuses are blown.

Method And Apparatus For Storage Of Test Results Within An Integrated Circuit

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US Patent:
61947385, Feb 27, 2001
Filed:
Feb 27, 1998
Appl. No.:
9/032417
Inventors:
Brett Debenham - Meridian ID
Kim Pierce - Meridian ID
Douglas J. Cutter - Fort Collins CO
Kurt Beigel - Boise ID
Fan Ho - Sunnyvale CA
Patrick J. Mullarkey - Meridian ID
Dien Luong - Boise ID
Hua Zheng - Fremont CA
Michael Shore - Boise ID
Jeffrey P. Wright - Boise ID
Adrian E. Ong - Pleasanton CA
Todd A. Merritt - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2358
US Classification:
257 48
Abstract:
An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

Method And Apparatus For Memory Array Compressed Data Testing

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US Patent:
59352639, Aug 10, 1999
Filed:
Jul 1, 1997
Appl. No.:
8/886195
Inventors:
Brent Keeth - Boise ID
Troy A. Manning - Meridian ID
Chris G. Martin - Boise ID
Kim M. Pierce - Meridian ID
Wallace E. Fister - Boise ID
Kevin J. Ryan - Eagle ID
Terry R. Lee - Boise ID
Mike Pearson - Boise ID
Thomas W. Voshell - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1100
US Classification:
714718
Abstract:
A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.
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Kim Susanne Pierce from Boise, ID, age ~65 Get Report