Khin A Lay

6490005, Dec 3, 2002

Jun 30, 2000

09/607493

James Chow - Palo Alto CA
Kenny Wen - San Jose CA
Khin Lay - Santa Clara CA

STMicroelectronics, Inc. - Carrollton TX

H03M 112

348572, 348574

An analog-to-digital converter (ADC) ( ) for sampling high speed video signals includes Pre-amplifiers ( ) electrically coupled to Post-amplifiers ( ) that are electrically coupled to output latches ( and ). A sampling clock signal ( ) clocks the output latches ( and ) to sample an input analog electronic signal to provide a digital representation thereof. The ADC ( ) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers ( ) during a video signal horizontal blanking time period. The ADC ( ) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers ( ) increasing bit resolution. The ADC ( ) includes wired interconnect interpolation between the Pre-amplifiers ( ) and Post-amplifiers ( ) and between the Post-amplifiers ( ) and the output latches ( and ).

20030118138, Jun 26, 2003

Dec 21, 2001

10/037967

James Chow - Palo Alto CA, US
Khin Lay - San Jose CA, US
Kenny Wen - San Jose CA, US

H04L007/00

375/355000

A differential data sampling circuit is provided for sampling an input signal line with precise timing so as to provide reduced sensitivity to noise. The differential data sampling circuit includes a latch circuit for initially sampling a differential data signal in response to a first strobe signal. The latch circuit operates to rapidly capture the signal level present on the input signal line. The output of the latch circuit is then sampled by a strobe circuit in order to capture and hold the output of the latch circuit based on a second strobe signal. In preferred embodiments, the latch circuit has a high input impedance. A digital data receiver including such a differential data sampling circuit is also provided.