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Khaled Mohamed Labib

from San Jose, CA
Age ~57
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Also known as:
Khaled M Labib, Khaled Labid
Phone and address:
3324 Lynn Oaks Dr, San Jose, CA 95117
(408) 680-6973
Related to:
Jonathan A Labib, 32Remon N Labib, 34Lucille Hamel, 92Adel Elkadi, 59Ibrahim Hamadeh, 32Adam Hamadeh, 31
Connected to:
Ahmed F Labib, 53Aiman N Labib, 50Atef M Labib, 61Gina M Labib, 46Lina O Labib, 41Mahir Labib, 29Marina M Labib, 28Mark F Labib, 27Peter A Labib, 40Said Labib, 34

Khaled Labib Phones & Addresses

  • 3324 Lynn Oaks Dr, San Jose, CA 95117 (408) 680-6973
  • 2813 Forbes Ave, Santa Clara, CA 95051 (408) 249-2712
  • 2014 Acacia Ct, Santa Clara, CA 95050 (408) 249-2712
  • 3520 Tracy Dr, Santa Clara, CA 95051 (408) 249-2712
  • Sunnyvale, CA

Work

Company: Amcc Jan 2009 Position: Senior principal design engineer

Education

Degree: Ph.D. School / High School: University of California, Davis 1998 to 2005 Specialities: Engineering - Applied Science

Skills

Firmware • Microprocessors • Software Engineering • Communication Protocols • Programming Languages • Soc • Algorithms • Architecture • Operating Systems • Asic • Embedded Systems • Ic • Semiconductors • Verilog • Simulations • Device Drivers • Debugging • Application Specific Integrated Circuits • Functional Verification • Field Programmable Gate Arrays • Embedded Software • Hardware Architecture • Cmos • Rtl Design • Storage • C • Linux • Very Large Scale Integration • Technical Leadership • Solid State Drive • Assembly Language • C Language • Emulation • Device Driver • Cpu Architecture • Networking Protocols • Storage Architecture • Revision Control • Scripting Languages • Fpga Prototyping • Flash Technology • Storage Interfaces • Compilers and Tool Chain • Cmos Image Sensors Camera • Asic Development Flow • Executive Management • Design Verification Testing • Perl • Cross Functional Team Leadership • Eda

Ranks

Certificate: Six Sigma - Green Belt

Industries

Semiconductors

Resumes

Resumes

Khaled Labib Photo 1

Vice President Of Engineering

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
AMCC since Jan 2009
Senior Principal Design Engineer
MagnaChip Semiconductors Jul 2007 - Oct 2008
Director, Software Engineering
Hifn 2006 - 2007
Manager, Software Engineering
Toshiba America Electronic Components 1997 - 2006
Senior Manager, System Validation and Emulation
Samsung Semiconductor Apr 1996 - Jul 1997
Software Development Engineer
Education:
University of California, Davis 1998 - 2005
Ph.D., Engineering - Applied Science San Jose State University 1993 - 1995
M.Sc., Computer Engineering Cairo University 1984 - 1989
B.Sc., Electronics and Communications Engineering
Skills:
Firmware
Microprocessors
Software Engineering
Communication Protocols
Programming Languages
Soc
Algorithms
Architecture
Operating Systems
Asic
Embedded Systems
Ic
Semiconductors
Verilog
Simulations
Device Drivers
Debugging
Application Specific Integrated Circuits
Functional Verification
Field Programmable Gate Arrays
Embedded Software
Hardware Architecture
Cmos
Rtl Design
Storage
C
Linux
Very Large Scale Integration
Technical Leadership
Solid State Drive
Assembly Language
C Language
Emulation
Device Driver
Cpu Architecture
Networking Protocols
Storage Architecture
Revision Control
Scripting Languages
Fpga Prototyping
Flash Technology
Storage Interfaces
Compilers and Tool Chain
Cmos Image Sensors Camera
Asic Development Flow
Executive Management
Design Verification Testing
Perl
Cross Functional Team Leadership
Eda
Certifications:
Six Sigma - Green Belt

Publications

Us Patents

Optimization Of Parameters For Synthesis Of A Topology Using A Discriminant Function Module

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US Patent:
20220222404, Jul 14, 2022
Filed:
Mar 1, 2022
Appl. No.:
17/683361
Inventors:
- Campbell CA, US
Khaled LABIB - San Jose CA, US
Assignee:
ARTERIS, INC. - Campbell CA
International Classification:
G06F 30/31
G06F 30/398
G06F 30/367
G06F 30/327
Abstract:
A tool is disclosed that includes a discriminant module. The discriminant module finds one configuration, which is selected from many different possible and legal configurations, that is optimal. The optimal configuration is translated into a set of optimized parameters (identified from the library of parameters that the user can select from) and provided to the designer. The designer reviews (and can manually revise or change) the optimized parameters. The optimized parameters are translated into engineering parameters. The engineering parameters are passed, as an input, to the RTL generation module. The RTL generation module produces the RTL description of the hardware function that is optimal and meets the designer's defined requirements.

Generation Of Hardware Design Using A Constraint Solver Module For Topology Synthesis

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US Patent:
20220207226, Jun 30, 2022
Filed:
Dec 26, 2020
Appl. No.:
17/134384
Inventors:
- Campbell CA, US
Khaled LABIB - San Jose CA, US
Assignee:
ARTERIS, INC. - Campbell CA
International Classification:
G06F 30/367
G06F 30/327
G06F 30/398
G06F 30/33
Abstract:
In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that can automatically find the best legal configuration that will be optimal with respect to a given set of requirements or metrics, such as: area, timing, and power. A designer defines the metrics or requirements, which represent the functional needs. A designer typically selects a set of parameters from a group of parameters available to user, which are user selectable parameters. The best parameters, from which the user can select parameters, are identified, and provided to the user. A constraint solver module ensures all rules are enforced and finds all legal parameters that fulfil the user intent. The constraint solver module generates configurations that meet the requirements and are legal configurations.

System And Method To Determine Optimal Path(S) And Use Load Balancing In An Interconnect

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US Patent:
20220368637, Nov 17, 2022
Filed:
Jul 27, 2022
Appl. No.:
17/875359
Inventors:
- Campbell CA, US
Syed Ijlal Ali SHAH - Austin TX, US
Khaled LABIB - San Jose CA, US
Assignee:
ARTERIS, INC. - Campbell CA
International Classification:
H04L 47/125
H04L 45/121
H04L 45/24
H04L 45/128
Abstract:
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using an interconnect, such as a network-on-chip (NoC). Some embodiments of the invention apply to a class of interconnects that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the interconnect. Slaves (targets or destinations) service the data packets or traffic traveling through the interconnect. The interconnect includes switches and links that are part of a path. Additionally, one or more optimal routes, which is defined by the system, move the traffic in a way that avoids deadlock scenarios.

System And Method For Synthesis Of A Network-On-Chip To Determine Optimal Path With Load Balancing

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US Patent:
20210320869, Oct 14, 2021
Filed:
Apr 9, 2020
Appl. No.:
16/845056
Inventors:
- Campbell CA, US
Syed Ijlal Ali SHAH - Austin TX, US
Khaled LABIB - San Jose CA, US
Assignee:
ARTERIS, INC. - Campbell CA
International Classification:
H04L 12/803
H04L 12/735
H04L 12/707
H04L 12/727
Abstract:
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using a Network-on-Chip (NoC). More precisely, some embodiments of the invention apply to a class of NoCs that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the NoC. Slaves (targets or destinations) service the data packets or traffic traveling through the NoC. The NoC includes switches and links. Additionally, the optimal routes defined by the system includes moving the traffic in a way that avoids deadlock scenarios.
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Khaled Mohamed Labib from San Jose, CA, age ~57 Get Report