Kevin M Mcgrath

7058791, Jun 6, 2006

Apr 2, 2001

09/824988

William A. Hughes - Burlingame CA, US
Kevin J. McGrath - Los Gatos CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9/44

712 43, 712229

A processor generates a mode indication based on two or more other indications. The mode indication is indicative of whether or not a particular mode is active in the processor. Each indication is stored in a storage location which is addressable via a different instruction. In one embodiment, a long mode in which a 64 bit operating mode is selectable in addition to 32 bit and 16 bit modes may be activated via a long mode active indication. The long mode active indication may be generated by the processor, and may indicate that long mode is active if paging is enabled and a long mode enable indication indicates that long mode is enabled. In this manner, long mode may be activated after paging is enabled (with a set of long mode page tables indicated by the page table base address).

7418584, Aug 26, 2008

Feb 25, 2005

11/066752

Alexander C. Klaiber - Mountain View CA, US
Geoffrey S. Strongin - Austin TX, US
Kevin J. McGrath - Los Gatos CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

712229, 712244

In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the intercept indication and further responsive to detecting the event, execution circuitry in the processor is configured to exit the guest. In another embodiment, a method comprises: detecting an event that would cause a processor to transition to a first mode, wherein first code is to be executed in the first mode; and causing the first code to be executed in a guest responsive to the detecting. In still another embodiment, a computer accessible medium comprising instructions which when executed in response to detecting the event, cause the first code to be executed in a guest.

7754197, Jul 13, 2010

Oct 16, 2003

10/686937

Bin Wu - Foxboro MA, US
Kevin P. McGrath - Alpharetta GA, US
Jaeho Kim - Roswell GA, US
Bao Trong Kim - Decatur GA, US
Sharon Linda Greene - Canton GA, US
Yanbin Huang - Roswell GA, US
Kaiyuan Yang - Cumming GA, US

Kimberly-Clark Worldwide, Inc. - Neenah WI

B01D 53/34
A01N 59/00
A01N 59/16
A01N 59/20
A61K 33/00
A61K 33/38
A61K 33/34
A61K 33/32
A61K 33/26
A61K 33/24

424 762, 424600, 424617, 424618, 424630, 424639, 424641, 424646, 424649

A method for reducing odor is provided. The method comprises forming a coordination complex between a transition metal and a polydentate compound, and contacting the coordinated complex with an odorous compound. The transition metal provides one or more active sites for capturing the odorous compound. In some embodiments, the polydentate compound may be a polyalkylimine, such as polyethyleneimine, polypropyleneimine, or a dendrimer thereof.

8127098, Feb 28, 2012

Feb 25, 2005

11/066873

Alexander C. Klaiber - Mountain View CA, US
Kevin J. McGrath - Los Gatos CA, US
Hongwen Gao - Union City CA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 12/14

711163, 711205, 711151

In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing in a processor; determining that the write attempts to establish a first mode in the processor in which privilege level protection is disabled and paging is disabled; and causing the guest to execute in a second mode in which privilege level protection is disabled and paging is enabled instead of the first mode. A computer accessible medium comprising instruction implementing at least a portion of the method is also described.

8178081, May 15, 2012

Jul 13, 2010

12/835418

Bin Wu - Foxboro MA, US
Kevin P. McGrath - Alpharetta GA, US
Jaeho Kim - Roswell GA, US
Bao Trong Do - Decatur GA, US
Sharon Linda Greene - Canton GA, US
Yanbin Huang - Roswell GA, US
Kaiyuan Yang - Cumming GA, US

Kimberly-Clark Worldwide, Inc. - Neenah WI

A61L 15/46
A61L 9/01
A61L 9/12
C08F 8/42
A61M 16/06

424 761, 12820312, 424489, 424630, 424639, 424646, 424649, 525371, 604360

A method for reducing odor is provided. The method comprises forming a coordination complex between a transition metal and a polydentate compound, and contacting the coordinated complex with an odorous compound. The transition metal provides one or more active sites for capturing the odorous compound. In some embodiments, the polydentate compound may be a polyalkylimine, such as polyethyleneimine, polypropyleneimine, or a dendrimer thereof.

20120311269, Dec 6, 2012

Jun 3, 2011

13/153102

Gabriel H. Loh - Bellevue WA, US
Jaewoong Chung - Bellevue WA, US
Nuwan Jayasena - Sunnyvale CA, US
Steve Reinhardt - Vancouver WA, US
James O'Connor - Austin TX, US
Kevin McGrath - Los Gatos CA, US

G06F 12/08

711133, 711E12017

An apparatus is disclosed for caching memory data in a computer system with multiple system memories. The apparatus comprises a data cache for caching memory data. The apparatus is configured to determine a retention priority for a cache block stored in the data cache. The retention priority is based on a performance characteristic of a system memory from which the cache block is cached.

20130155079, Jun 20, 2013

Dec 14, 2011

13/325339

Robert Scott HARTOG - Windemere FL, US
Nuwan JAYASENA - Sunnyvale CA, US
Mark LEATHER - Los Gatos CA, US
Michael MANTOR - Orlando FL, US
Rex McCRARY - Oviedo FL, US
Kevin McGRATH - Los Gatos CA, US
Sebastien NUSSBAUM - Lexington MA, US
Philip J. ROGERS - Pepperell MA, US
Ralph Clay TAYLOR - Deland FL, US
Thomas R. WOLLER - Austin TX, US

G06T 1/00

345522

Provided is a method for processing a command in a computing system including an accelerated processing device (APD) having a command processor. The method includes executing an interrupt routine to save one or more contexts related to a first set of instructions on a shader core in response to an instruction to preempt processing of the first set of instructions.

54559189, Oct 3, 1995

Feb 27, 1995

8/394554

Terry Fowler - Mountain View CA
Kevin McGrath - Hayward CA
Terry Goode - Sunnyvale CA
Mark Schneckloth - San Jose CA

Electronic Arts, Inc. - San Mateo CA

G06F 300
G06F 900

395375

In a computing system having a data source, a memory, and a central processing unit (CPU), data is transferred from the data source to the memory by first monitoring signals from the CPU to determine whether data transfer is desired. If data transfer is desired, an optimized instruction set is generated which is specifically designed to cause the CPU to carry out the data transfer in an optimal manner. This optimized instruction set is sent to the CPU and is executed thereby to transfer the data quickly and efficiently. An apparatus for carrying out the above method comprises a determiner, an instruction generator, and a coupling circuit. The determiner monitors address and control signals from the CPU to determine whether data transfer is desired. In response to a determination that data transfer is desired, the determiner generates a run control signal. The instruction generator receives from the data source the data to be transferred and a destination address in the memory in which the data is to be stored, and generates an optimized instruction set using this data and address.