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Kevin M Koschoreck

from Ridgefield, WA
Age ~53
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Also known as:
Kevin K
Related to:
Kate KoschoreckAudrey Axtolis, 86Brittany J Axtolis, 29Jason Axtolis, 53
Connected to:
Kate Koschoreck, 69Walter L Kosciak, 61Brian Koscianski, 39Halina A Koscianska, 69James Koscianski, 70Melinda K Koscianski, 62Dennis R Koscicki, 80Bianca R Koscielski, 44Brian M Koscienski, 53Bronson B Koscielski, 34

Kevin Koschoreck Phones & Addresses

  • Ridgefield, WA
  • 13123 Clearview Way, Tigard, OR 97223 (503) 524-8565 (503) 747-3785 (503) 524-7902
  • Portland, OR
  • Cannon Beach, OR
  • Tolovana Park, OR
  • Beaverton, OR
  • Boxford, MA
  • 13123 SW Clearview Way, Portland, OR 97223 (503) 747-3785

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Emails

k***[email protected]

Resumes

Resumes

Kevin Koschoreck Photo 1

Senior Design Engineer At Nvidia

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Position:
Senior Design Engineer at NVIDIA
Location:
Portland, Oregon Area
Industry:
Computer Hardware
Work:
NVIDIA
Senior Design Engineer
Ambric 2003 - 2008
Senior Design Engineer
Geocast Network Systems 1998 - 2002
Senior Design Engineer
PMC-Sierra 1998 - 1999
Senior Design Engineer
Intel Corporation 1996 - 1998
Design Engineer
Education:
University of Illinois at Urbana-Champaign 1989 - 1993
BS, Computer Engineering
Kevin Koschoreck Photo 2

Kevin Koschoreck

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Kevin Koschoreck
Principal, Secretary
OUTSRC, INC
389 · Employment Service · Management Consulting Services
13123 Swclearview Way, Portland, OR 97223
13123 SW Clearview Way, Portland, OR 97223
(503) 524-8565

Publications

Us Patents

Clock Generation For Multiple Clock Domains

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US Patent:
7945803, May 17, 2011
Filed:
Jul 26, 2006
Appl. No.:
11/460231
Inventors:
Anthony Mark Jones - Beaverton OR, US
Kevin M. Koschoreck - Beaverton OR, US
Assignee:
Nethra Imaging, Inc. - Santa Clara CA
International Classification:
G06F 1/04
US Classification:
713501, 713500, 713502
Abstract:
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.

Instruction Cache Power Reduction

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US Patent:
20130179640, Jul 11, 2013
Filed:
Jan 9, 2012
Appl. No.:
13/346536
Inventors:
Aneesh Aggarwal - Portland OR, US
Ross Segelken - Portland OR, US
Kevin Koschoreck - Tigard OR, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 12/12
US Classification:
711136, 711E12071
Abstract:
In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

Branch Prediction Power Reduction

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US Patent:
20130290640, Oct 31, 2013
Filed:
Apr 27, 2012
Appl. No.:
13/458542
Inventors:
Aneesh Aggarwal - Portland OR, US
Ross Segelken - Portland OR, US
Kevin Koschoreck - Tigard OR, US
Paul Wasson - Tigard OR, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/30
G06F 12/08
US Classification:
711125, 712205, 712E09016, 711E1202
Abstract:
In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Dual Mode Bus Bridge For Computer System

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US Patent:
61346225, Oct 17, 2000
Filed:
Jan 26, 1998
Appl. No.:
9/013777
Inventors:
Suvansh Kapur - Portland OR
Kevin Koschoreck - Tigard OR
Srinand Venkatesan - Beaverton OR
D. Michael Bell - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1338
US Classification:
710128
Abstract:
A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.
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Kevin M Koschoreck from Ridgefield, WA, age ~53 Get Report